Paper
12 May 2005 Technology qualification for 65-nm node
Author Affiliations +
Abstract
IC manufacturing at 65 nm node requires careful selection of imaging technology. To select appropriate approach, a wide range of impacts has to be considered. In particular, imaging, mask, and resist technologies all contribute to final CD control of the features patterned and their imaging latitude during IC manufacture. To select imaging strategy, we conducted simulation analysis of dry ArF, dry F2, and immersion ArF imaging technologies. During the selection process, each technology has to be evaluated at its imaging optimum defined in terms of projection lens NA and illuminator design as well as the mask design details; such analysis has to be specific to the requirements of the IC design critical levels. One of the key technology characteristics is the imaging tool impact on patterned level. This impact can be quantified by the projection lens aberration residue and its flare, both dependent on the image location. Introduction of aberration and flare signatures into the imaging analysis enables definition of tool performance metric common to the entire image field, and it spotlights across-field imaging tradeoffs. In addition to these factors (i.e. the imaging technology- and the tool-related impact), the impact of wafer stack on image formation in resist has to be considered. In particular, Fresnel losses, resist photochemistry, and optical path differences of diffraction orders in dense medium have to be accounted for. Such approach leads to estimates of resist refraction and contrast on the formation of critical features. This review presents comprehensive analysis of all key factors driving imaging latitude of critical levels at 65 nm node. These factors were representing impacts of imaging strategy, mask and resist technologies. The analysis presented below spotlights imaging tradeoffs of dry ArF, dry F2, and immersion ArF imaging technologies.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jacek K. Tyminski and Toshiharu Nakashima "Technology qualification for 65-nm node", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); https://doi.org/10.1117/12.600246
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Imaging technologies

Photomasks

Picosecond phenomena

Process control

Manufacturing

Reticles

Phase shifts

RELATED CONTENT

Patterning 80 nm gates using 248 nm lithography an...
Proceedings of SPIE (September 14 2001)
Forbidden pitches for 130-nm lithography and below
Proceedings of SPIE (July 05 2000)
Aberration budget in extreme ultraviolet lithography
Proceedings of SPIE (March 20 2008)

Back to Top