FPGA-based floating-point datapath design for geometry processing

Shanzhen Xing; William W.H. Yu

doi:10.1117/12.327034

8 October 1998 FPGA-based floating-point datapath design for geometry processing

Shanzhen Xing, William W.H. Yu

Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327034
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States

Abstract

Geometry processing comprises of a great many computationally intensive floating-point operations. Real- time graphics systems generally use application-specific custom designed parallel hardware to provide the high performance computation power. When designing a graphics engine on a FPGA-based configurable computing system, cost- effectiveness is important. This paper investigates and proposes a cost-effective FPGA-based floating-point datapath for geometry process. It is designed to be a basic building block for FPGA-based geometry processors. The implemented datapath operates at a frequency of 6.25 Mhz and has an average floating-point operation time of 10.2 microseconds.

Citation Download Citation

Shanzhen Xing and William W.H. Yu "FPGA-based floating-point datapath design for geometry processing", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327034

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