IEICE Trans - Design and Evaluation of a 54<cd0215f.gif>54-bit Multiplier Based on Differential-Pair Circuitry

Design and Evaluation of a 54

54-bit Multiplier Based on Differential-Pair Circuitry

Akira MOCHIZUKI
Hirokatsu SHIRAHAMA
Takahiro HANYU

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.683-691
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.683
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword:
differential-pair circuit, current-mode circuit, multiple-valued logic,

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Summary:
This paper presents a high-speed 54

54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm² active area.