Temperature-dependent transport and hysteretic behaviors induced by interfacial states in MoS₂ field-effect transistors with lead-zirconate-titanate ferroelectric gating

The MoS₂ flakes were mechanically exfoliated from a bulk ingot (SPI Supplies) and transferred onto the PZT/Pt/Ti/SiO₂/Si substrates with a 260 nm-thick Pb(Zr_0.4Ti_0.6)O₃ (PZT) layer prepared by a sol-gel process. The Pt layer underneath the PZT films served as the gate electrode, while the PZT films served as the gate dielectric. After the transfer of the MoS₂ flakes, electron-beam lithography was used to pattern source/drain contacts, followed by electron-beam evaporation of 20/50 nm Cr/Au electrodes and a lift-off process. A schematic of the MoS₂-PZT FET devices is shown in figure 1(a). An optical microscope image of the MoS₂-PZT FET devices is shown in the inset of figure 1(b) with the channel length L ∼ 200 nm and width W ∼ 30 μm and the width of the contact bars is about 2 μm.

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Raman spectroscopy using a wavelength of 532 nm (RM-1000, Renishaw) was used to confirm the MoS₂ sheet with few layers. In order to verify the thickness of this MoS₂ sheet, the microstructure and morphology of the MoS₂-PZT FETs were observed by atomic force microscopy (AFM, SPA 500, Seiko Instruments Inc.) with taping mode. The polarization–voltage (P–V) characteristics were measured by using a ferroelectric test system (Multiferroics, Radiant Company) with a temperature increasing from 300 to 380 K. The temperature-dependent electrical measurements of the device were conducted by an Agilent B1500A semiconductor parameter analyzer with a variable temperature probe station. The test temperature ranged from 300 to 380 K in our experiments.

The basic electrical properties of such PZT-gated MoS₂ FETs have been reported in our previous published work [18]. In this paper, we further investigated the electrical performances of the MoS₂-PZT FETs with varying max-gate sweeping voltage (V_gmax) under different temperature (T). Figure 2 presents the I_ds–V_gs curves of the device under V_gmax of 4, 6, 8 and 10 V, respectively, with temperature ranging from 300 to 380 K. Each cyclic voltage sweeping from −V_gmax to V_gmax to −V_gmax is repeated and the resultant I_ds–V_gs loops show good reproducibility under different V_gmax. It is noted that the observed clockwise current hysteresis behaviors are opposite to the expected anticlockwise hysteresis behaviors arising from the polarization effects of the ferroelectric gate dielectric. The origin of the clockwise hysteresis behaviors can be attributed to the dynamic charge-trapping/de-trapping process in the interfacial states between MoS₂ and PZT films under the modulation of ferroelectric polarization. On one hand, as a typical oxide ferroelectric material, polycrystalline PZT is usually oxygen-deficient [26]. In the region near the interface between MoS₂ and PZT, there are more oxygen deficiencies than in the bulk. On the other hand, the oxygen/water molecules in the ambient absorbed on the surface of PZT films before MoS₂ exfoliated on it also contribute to the defects in the interfacial layer. Moreover, some ionic impurities could be introduced during the solution preparation process of PZT films, which also accounted for the defects in the interfacial states. These defects include oxygen deficiencies, the oxygen/water molecules and ionic impurities bounded at on the surface of PZT films could act as electron traps which can dynamically respond to the change of ferroelectric polarization-induced built-in field under different V_gs. As shown in figure 1(d), the applied gate voltage V_gs induces an arrangement of dipoles in the PZT films, which causes a built-in electric field due to the polarization effect. The polarization slightly decreases to the remnant polarization P_r when V_gs is swept from a negative voltage to zero, which induces a large and stable electrostatic field through the interfacial layer between MoS₂ and PZT films. The electrons trapped in the interfacial states will obtain sufficiently large energy from the polarization field and be released into the MoS₂ channel under the downward ferroelectric polarization field, which results in a dramatic increase of drain current (as shown in figure 2).

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It can be seen from figure 3, that when V_gs sweeps from -V_gmax to 0 V, the electrons already trapped in the interfacial states can be released into the MoS₂ channel under the electrostatic field induced by downward polarization, which presents a de-trapping process. These de-trapped electrons moving into the n-type MoS₂ channel result in an n-doping effect. As shown in figure 3(a), before the V_gs reaches zero, the polarization intensity decreases slightly, which results in a stable built-in electric field. This stable polarization could build up a stable polarization filed, which would provide the dynamic charges with larger kinetic energy and drive more electrons into the MoS₂ channel. This indicates the accumulation of electrons in the MoS₂ channel and the dramatic increase in drain current, as shown in figure 2. When V_gs sweeps from 0 V to V_gmax, the polarization of PZT films decreases and is reversed to upward polarization, as shown in figure 3(b). During this process, the built-in ferroelectric field is reduced and the number of de-trapped electrons becomes less, which contributes to a balanced state between the charge-trapping and de-trapping process and indicates a saturated current. Once V_gs sweeps from V_gmax to 0 V, the electrons will be trapped again in the interfacial layer, which results in a drastic reduction of current, as shown in figure 3(c). And when V_gs sweeps from 0 to -V_gmax, the polarization can be reduced and the number of trapped electrons become less, as shown in figure 3(d). Therefore, the current of the n-type MoS₂ channel becomes small, representing the OFF state of MoS₂-PZT FETs. Above all, the dynamic charge-trapping/de-trapping process of interfacial states between PZT films and MoS₂ under the polarization effect of PZT films contributes to the reproducible clockwise hysteresis behaviors. As V_gmax increases from 4 to 10 V, the polarization of PZT films improves, inducing a faster trapping/de-trapping process and enlarged hysteresis behavior, as shown in figure 2. In this way, the modulation of gate voltage in the transport characteristics of MoS₂-PZT FETs has been achieved.

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It can also be found that with V_gmax values changing from 4 to 10 V, all the transfer curves exhibit the same change trends with varying T. It can be seen that the size of the hysteresis loop increases with the increasing T. In order to further study the influence of T on the electrical properties of MoS₂-PZT FETs, the max currents obtained at polarized saturation states when V_gs swept from -V_gmax to V_gmax are defined as the max drain current. The difference in V_gs that occurs at the current value corresponding to the midpoint of the maximum and minimum possible current values of the device is defined as the memory window (ΔV_M) as shown in figure 4(a). The max drain current is calculated from the transfer characteristics of MoS₂-PZT FETs as a function of the V_gmax and T in figure 4(b). It can be seen that the max drain current is 2.1 μA at 300 K when the V_gmax is 10 V. With the temperature rising to 380 K, the max drain current increases to 7.3 μA and similar behaviors can be found with V_gmax ranging from 4 to 10 V. The threshold voltage V_T is extracted from the onset of significant drain current conduction in the drain current transfer curves, as shown in figure 4(a). In the meantime, the threshold voltages with varying V_gmax and T follow the expected trend for an n-type semiconductor in figure 4(c). The threshold voltages from −V_gs to V_gs under different V_gmax follow in the same way to decrease to more negative values with the increase of temperature. We also extract the memory windows ΔV_M from the transfer curves for MoS₂-PZT FETs with varying temperature and V_gmax from 4 to 10 V, as shown in figure 4(d). It can be seen that the ΔV_M changes slightly with the increase of T under different V_gmax. The possible factors on the temperature-dependent electrical performances of MoS₂-PZT FETs may be the polarization of PZT films, the carrier transport characteristics in the MoS₂ channel, the change of contact resistances and the interfacial states between PZT and MoS₂. In order to find out the crucial factor, the related temperature-dependent measurements have been conducted and discussed below.

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In order to gain insight into the dependence of ferroelectric polarization on T, the P–V characteristics with T ranging from 300 to 380 K have been investigated, as shown in figure 5(a). As ferroelectrics, the pyroelectric coefficients of PZT films can be determined by the varying T, resulting in temperature-dependent polarization states. From figure 5(b), the remnant polarization (2P_r) has been plotted as a function of T, indicating that increasing T leads to a weakened polarization of PZT films. It is obviously the case that as the polarization becomes weakened, the current hysteresis loop induced by interfacial charge trapping/de-trapping under the polarization will be reduced (as discussed above). However, as shown in figure 2, it is opposite to the change of the polarization of PZT films with increasing T, which demonstrates that there are other temperature-dependent factors playing a major role. As a FET structure with a two 2-terminal (S/D) device configuration, the temperature dependence of contact resistances between S/D electrodes and the MoS₂ channel has been calculated from the output characteristics, with V_gs ranging from 0 to 8 V and T increasing from 300 to 380 K in PZT back-gated FETs with different channel lengths. The results show a slight change with the increase of temperature, as shown in figure 5(c), indicating that the thermally sensitive hysteresis behaviors do not originate from the change of contact resistances with the increasing T. Considering the dependence of carrier transport characteristics in the MoS₂ channel, the scattering mechanism has been found to be a critical factor. It has been reported that at temperatures below 100 K, temperature-independent mobility is limited by Coulomb scattering, whereas, at temperatures above 100 K, phonon-limited mobility decreases as a power law with increasing temperature [27]. Therefore, the current of MoS₂ should be reduced with the enhancement of phonon scattering when T increases from 300 to 380 K. However, this also goes against the observed temperature-dependent transport curves, as shown in figures 2 and 4. Therefore, it can be inferred that the temperature dependence of the interfacial states contributes to the enlargement of transport and hysteresis behaviors of MoS₂-PZT FETs. At the negative gate voltage, the charge de-trapping process will become more drastic to release more electrons to the MoS₂ channel at a faster speed with the increase of T, which results in a larger drain current and a more negative threshold voltage, as shown in figure 4. The process of electrons trapped again in the interfacial layer will also be enhanced with the increase of T, inducing a dramatic decline of drain current. Therefore, sets of transfer characteristics with different V_gmax have a similar dependence on temperature.

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Figure 6(a) shows the semilog plot of the transfer characteristics with gate voltage sweeping from −10 to 10 V and the temperature ranging from 300 to 380 K. The on current reaches 2.2 μA at T = 300 K and the corresponding current I_on/I_off ratio is over 10⁴. While for a temperature of 380 K, the on current is 7.3 μA at V_gs = 10 V and the corresponding current I_on/I_off ratio is over 10³. The I_on/I_off ratio shows a minor decrease as the temperature increases, while the total change of I_on/I_off ratio remains within 1 order of magnitude, as shown in figure 6(b). In the n-type MoS₂, the minority carriers (holes) have more sensitive temperature dependence than electrons. When V_gs is swept from positive to negative, the electrons trapping/de-trapping into/out of the interfacial states activated by increasing temperature become more dynamic, resulting in an increasing I_off and a decreasing I_on/I_off. Moreover, the output characteristics (drain-source current I_ds versus drain-source voltage V_ds) and their temperature dependence have also been investigated. The output characteristics (I_ds−V_ds) with V_gs ranging from 0 to 8 V at a step of 2 V at 300 K are shown in figure 6(c). Here, the curves show well-defined linear regimes at low biases and have a tendency toward saturation at high biases, indicating the typical pinch-off characteristics of n-type semiconductor FETs. Figure 6(d) shows the temperature dependence of the output characteristics with V_gs at 2 V and T increasing from 300 to 380 K, which indicates an increase of drain current due to the enhanced dynamic process of charge trapping/de-trapping with the increasing temperature.

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