If it's pinched it's a memristor

In his quest to develop an electrical lighting device that would replace the prevailing gas lamps, Sir Humphry Davy [5] built a two-terminal electrical device consisting of two oppositely-directed sharply-honed carbon rods, separated by a narrow air gap, as shown in figure 1(a) [6]. When Davy applied a very high dc voltage (more than 1000 V, generated by connecting more than a thousand Volta batteries in series) across his carbon-rod device in 1801 [5], barely a year after Alessandro Volta invented the battery, a very bright continuous electric arc discharges across the air gap, thereby heralding the world's first electric lamp² . Until only very recently, Davy's arc lamp had been misidentified as a light-emitting resistor. We now know it is in fact a memristor (Lin, et al [7]), as confirmed in a recent elaborate laboratory experiment at the University of Hong Kong, where a low-voltage scaled version of Davy's carbon rod arc discharge device was built (figure 1(b)), and the associated voltage and current waveforms were recorded (figure 1(d)). Observe the two waveforms are 'in-phase' in the sense that the current response i(t) = 0 whenever the input voltage v(t) = 0, which is the 'signature' of a memristor. The Lissajoux figure of the two waveforms (v(t), i(t)) in the i versus v plane in figure 1(e) shows the distinctive 'pinched hysteresis loop' fingerprint of a memristor³ .

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Sir Humphry Davy's arc lamp was the first written record of artificial lighting without using fire [5, 6]. His invention led quickly to the commercialization of various types of discharge tubes, as chronicled in a 1948 gem by Francis [8]. We have extracted the v–i Lissajoux figures of four discharge tubes from [8] and redrawn them in figure 2. Though unbeknownst to the makers of these discharge tubes, their measured Lissajoux figures bore the fingerprints of memristors.

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A careful analysis of discharge tubes in [7] and [8] had confirmed that the Lissajoux figures of the devices measured from any zero-mean periodic input voltages or currents are pinched hysteresis loops. It follows from our experimental definition that discharge tubes are memristors.

The earliest memristors using thin oxide films between 150 and 1000 Å thick were reported by Hickmott [9] in 1962, and by Argall [10] in 1968. Two pinched hysteresis loops from Hickmott [9] were redrawn with the missing components in the third quadrant (assuming the Lissajoux figure is odd-symmetric) and shown in figures 3(a) and (b). A pinched hysteresis loop from Argall [10] is redrawn and shown in figure 3(c). They all bore the 'Pinched hysteresis loop' hallmarks of memristors.

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As a proof of principle, a working memristor was synthesized, via a nonlinear circuit theory method developed in [3], and built using operational amplifiers (op amps) and transistors, as shown in figure 4. For a circuit engineer who needed a memristor device with the q versus φ curve shown on the bottom left of figure 4, for some novel applications, the black box in figure 4 would work just like a physical memristor, provided the operating frequency and dynamic range of all voltages and currents inside the black box are within the linear operating range of the op amps and transistors. Indeed, it was shown in [1] and [3] that a memristor with any prescribed q versus φ curve can be built using a resistor-to-memristor mutator as depicted in figure 5, and a nonlinear resistor having the same characteristic curve albeit replotted in the current i versus voltage v plane, which is a relatively easy task to build [3]. There are many ways to build a resistor-to-memristor mutator, the circuit inside the black box in figure 4 is only one possible realization. There are also many methods to build the 'surrogate' nonlinear resistor [3].

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It follows from the above scheme that memristors characterized by any prescribed q versus φ curve can be built with active circuit components, and a power supply, even if the desired memristor is passive, and therefore should not need an internal source of power. This power supply requirement is the main reason why the memristor had been relegated as an abstract device with no practical significance, until hp rekindled the interest with its titanium dioxide hp memristor in 2008 [11], a two-terminal passive nano device that measures less than 50 nm in diameter, and endowed with a non-volatile memory.

The seminal 2008 Nature paper has triggered unprecedented worldwide interests from both industry and academia, with publications increasing at an exponential rate. Most recently an 8 nm × 8 nm memristor was reported in [56], and a 1 nm memristor can be expected in the near future. For a state-of-the-art review, the reader is referred to three recent Special Issues on memristors, namely, Applied Physics A: Material Science and Processing (vol. 102, 2011), Proceedings of the IEEE (vol. 100, 2012), and Nanotechnology (vol. 24, 2013).

From the historical perspective, we end this section with the following quotation from the last paragraph (page 519) of [1]:

Indeed, in the same year (1971), M Kikuchi et al had published a paper in the journal Solid State Communications [12] where we reproduced the top of the paper below.

Kikuchi et al must have been flabbergasted by the strange current versus voltage hysteresis loop shown in figure 2 of their paper, which differs distinctly from conventional hysteresis loops from magnetic cores. Obviously sensing the importance of this new peculiar 'pinched' v–i loop, they added the adjectival name (LETTER '8') to the title of their paper. The following year, a review paper by H K Henisch on 'Amorphous Semiconductor Switching' confirms the generic feature of 'pinched' hysteresis loops for a class of memory devices dubbed 'ovonic memory switches', as depicted in figure 6(b) [13].

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This subsection exhibits a cornucopia of pinched hysteresis loops measured from real memristor devices, kicked off by the influential paper by Beck et al [14] published at the dawn of the new millennium. They are ordered not chronologically, but in accordance with certain similar features that can be emulated by simple mathematical equations and circuit models. Figure 7 presents 6 typical pinched hysteresis loops sampled from the following papers and redrawn in color:

• Figure 7(a): S L Johnson, et al 'Memristive switching of single-component metallic nanowires,' (2010) [15].
• Figure 7(b): R Waser, 'Resistive non-volatile memory devices,' (2009) [16].
• Figure 7(c): A Chanthbouala, et al 'A ferroelectric memristor,' (2012) [17].
• Figure 7(d): F Nardi, et al 'Complementary Switching in Oxide-Based Bipolar Resistive-Switching Random Memory,' (2013) [18].
• Figure 7(e): A Beck, et al 'Reproducible switching effect in thin oxide films for memory applications,' (2000) [14].
• Figure 7(f): T Sakamoto, et al 'Nanometer-scale switches using copper sulfide,' (2003) [19].

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Figure 8 presents six generic features of pinched hysteresis loops sampled from the following papers and redrawn in color:

• Figure 8(a): T H Kim, et al 'Nanoparticle Assemblies as Memristors,' (2009) [20]
• Figure 8(b): Y Yang, et al 'Complementary resistive switching in tantalum oxide-based resistive memory devices,' (2012) [21].
• Figure 8(c): K Szot, et al 'TiO₂-a prototypical memristive material,' (2011) [22].
• Figure 8(d): T Hino, et al 'Atomic Switches: atomic-movement-controlled nanodevices for new types of computing,' (2011) [23].
• Figure 8(e): S H Jo, et al 'Programmable resistance switching in nano scale two-terminal Devices,' (2011) [24].
• Figure 8(f): M D Pickett, et al 'A scalable neuristor built with Mott memristors,' (2012) [25].

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The family of pinched hysteresis loops exhibited in figures 7 and 8 are merely samples from publications that exhibit certain common morphologies. Unlike some devices such as those reported in [53] where a realistic physical model exists but did not include a pinched hysteresis loop in the v–i plane in linear scale, these samples are chosen for pedagogical reasons and do not imply superior performance over other uncited devices.

The memristors listed in figures 7 and 8 are made from inorganic semiconductors or amorphous materials. Figure 9 shows an example of a pinched hysteresis loop measured from a memristor made from an organic material [26]. Unlike the preceding pinched hysteresis loops, note that the 'pinched' point is not at the origin, but nearby. Such offsets are usually observed from memristors made from organic materials and/or biomaterials. This departure from the original definition of memristors can be modelled by adding parasitic circuit elements and/or batteries [27]. We will henceforth refer to such memristors with a pinched point located near but not on the origin (v, i) = (0, 0) as an imperfect memristor.

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Many biological systems exhibit memristive behaviors. Figure 10 shows the current response when a sinusoidal voltage is applied to the ventral forearm as depicted in figure 10(a). The conductivity of the skin is often found to increase with the passage of current. This well-known phenomenon has been reported in [28] and can be explained by the electro-osmotic transport of fluid through pores in the skin, mostly through the sweat ducts. The physical mechanism responsible for the conductivity modulation in sweat pores has been reported in [29]. Applying a current across a sweat duct turns the skin into a memristor. In particular, conductive fluid flowing up the sweat pore helps the current to flow across it as illustrated in figure 10(b). Conversely, conductive fluid flowing down the sweat pore would increase the skin resistance. A typical pinched hysteresis loop in the v versus i plane measured from the set-up in figure 10(a) is shown in figure 10(c). Figure 10(d) shows a non-periodic current response during a transient regime upon application of a sinusoidal voltage. Observe that even though the current is not periodic, the current waveform (blue) i(t) passes through zero at the same times as the periodic sinusoidal voltage waveform (red) v(t), which is the signature of a memristor. Indeed, such phenomenon implies that our body is covered with memristors [29].

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Another biological system which behaves like memristors is the Amoeba (slime mould). A recent experiment reported in [30] clearly shows a pinched hysteresis loop when a slow periodic voltage is applied to an amoeba via a pair of silver wire electrodes as shown in figure 11. Note that the pinched point is located not at, but near, the origin (v, i) = (0, 0).

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Many plants also exhibit memristive behaviors. Figure 12 shows the pinched hysteresis loop measured by applying a very slow sinusoidal voltage to a leaf of the venus flytrap plant [31], via a pair of Ag/Agcl⁺ electrodes. Observe the pinched point of the hysteresis loop is located not at, but near, the origin.

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A similar experiment on the Mimosa Pudica plant also shows a pinched hysteresis loop in figure 13 [31].

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Figure 14(a) shows a pair of bimorph coils attached between a pair of electrodes (memristor terminals) spaced about 200 μm apart. The dual coil was fabricated with a 30 nm thick layer (yellow) of cromium sitting on top of a 150 nm thick layer of vanadium dioxide (green) [32]. Application of a 3.1 V dc voltage across the two memristor terminals induces a rapid and powerful mechanical recoil resulting from a sudden decrease in the curvature of the coils and a corresponding increase in the coil diameter due to Joule heating. As shown in figure 14(b), the coil diameter increases with a corresponding decrease in the number of spiral turns because the length of the stretched wire remains unchanged. A tiny object placed in the center 'basket' notch will be hurled away like a catapult [32] with a force 1000 times more powerful than a human muscle of comparable size. In particular, this two-terminal device can catapult objects 50 times heavier than itself over a distance five times its length, and at a speed faster than the blink of an eye. A measurement of its current versus voltage characteristic shows a pinched hysteresis loop whose lobe area shrinks as the excitation frequency of the applied sinusoidal voltage increases, as depicted in figure 14(c). All of these observations bore the fingerprints of a memristor. Observe that the pinched point of the hysteresis loop in figure 14(c) of this micro catapult memristor is located at the origin (v, i) = (0, 0).

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An Extended Memristor is defined in table 1 (page 11).

Table 1.  Extended Memristor

A Generic Memristor is defined in table 2 (page 12).

Table 2.  Generic Memristor

An Ideal Memristor is defined as in table 3 (page 12).

Table 3.  Ideal Memristor

2.3.1. Memristor siblings

Every ideal memristor can be recast into a Generic Memristor with a scalar state variable x defined via a differentiable one-to-one function, in three simple steps as presented in table 4 (page 14).

Table 4.  How to Create Ideal Generic Memristors

Since the function $x=\hat{x}(q)$ in (8a) (resp., $x=\hat{x}(\varphi )$ in (8b)) can be chosen to be any differentiable one-to-one function, it follows that every Ideal Memristor has an uncountable number of memristor siblings that would give the same voltage response to a given input current i(t) (resp., the same current response to a given input voltage v(t)). Indeed, every Ideal Memristor is the mother of an infinite family of equivalent Generic Memristors.

2.3.2. Ideal generic memristor

We will henceforth refer to a small subclass of Generic Memristors as Ideal Generic Memristors if, and only if

Given a Generic Memristor described by (12a), or (12b), how does one determine whether it can be given the accolate of an 'Ideal' Generic Memristor ? The answer is to recast the second equation in (12a) and (12b) into the form:

$$\begin{eqnarray}&&\frac{{\rm d}x}{\hat{f}(x)}=i{\mkern 1mu} {\mkern 1mu} {\rm d}t,\end{eqnarray} \tag{ 13a }$$

$$\begin{eqnarray}&&\frac{{\rm d}x}{\hat{g}(x)}=v\;{\rm d}t.\end{eqnarray} \tag{ 13b }$$

Integrating both sides of (13a ) and (13b ), we obtain

$$\begin{eqnarray}&&\mathop{\underbrace{\int \left[ \frac{1}{\hat{f}(x)} \right]{\rm d}x}}\limits_{F(x)} = \mathop{\underbrace{\int i\;{\rm d}t}}\limits_{q},\end{eqnarray} \tag{ 14a }$$

$$\begin{eqnarray}&&\mathop{\underbrace{\int \left[ \frac{1}{\hat{g}(x)} \right]{\rm d}x}}\limits_{G(x)}= \mathop{\underbrace{\int v\;{\rm d}t}}\limits_{\varphi }.\end{eqnarray} \tag{ 14b }$$

It follows from (14a ) and (14b ) that this Generic Memristor is an Ideal Generic Memristor if, and only if, F(x) (resp. G(x)) is a one-to-one function, in which case, we can rewrite (14a ) (resp., (14b )) via its inverse function; namely⁴ ,

$$\begin{eqnarray}&&x={{F}^{-1}}(q)\triangleq \hat{x}(q),\end{eqnarray} \tag{ 15a }$$

$$\begin{eqnarray}&&x={{G}^{-1}}(\varphi )\triangleq \hat{x}(\varphi ),\end{eqnarray} \tag{ 15b }$$

where $\hat{x}(q)$ (resp., $\hat{x}(\varphi )$) is the differentiable one-to-one function from (8a) (resp., (8b)).

We will end this section with an example for illustrating the above simple procedure for creating generic memristor siblings from an ideal memristor.

Example:  Creating an Ideal Generic Memristor Sibling

Step 1. Choose any constitutive relation of an ideal memristor:

For this example, let us choose

$$\begin{eqnarray}&&\varphi =q+\frac{1}{3}{{q}^{3}}\triangleq \hat{\varphi }(q).\end{eqnarray} \tag{ 16 }$$

Step 2. Choose an arbitrary differentiable one-to-one function:

For this example, let us choose

$$\begin{eqnarray}&&x={{q}^{3}}\triangleq \hat{x}(q).\end{eqnarray} \tag{ 17 }$$

and its inverse

$$\begin{eqnarray}&&q={{x}^{1/3}}\triangleq {{\hat{x}}^{-1}}(x).\end{eqnarray} \tag{ 18 }$$

Step 3. Applying (9a) to (16)

$$\begin{eqnarray}&&R(x)={{\left. \frac{{\rm d}\hat{\varphi }(q)}{{\rm d}q} \right|}_{q={{x}^{1/3}}}}={{\left. \left( 1+{{q}^{2}} \right) \right|}_{q={{x}^{1/3}}}}=1+{{x}^{2/3}}.\end{eqnarray} \tag{ 19 }$$

Step 4. Applying (11a) to $\hat{x}(q)$ in (17):

$$\begin{eqnarray}&&\hat{f}(x)={{\left. \frac{{\rm d}{\mkern 1mu} \hat{x}(q)}{{\rm d}q} \right|}_{q=x{{}^{1/3}}}}={{\left. 3\;{{q}^{2}} \right|}_{q=x{{}^{1/3}}}}=3\;x{\mkern 1mu} {{{\mkern 1mu} }^{2/3}}.\end{eqnarray} \tag{ 20 }$$

Step 5. Substitute (19) for R(x) and (20) for $\hat{f}(x)$ in (12a) to obtain the following Ideal Generic Memristor:

We end section 2 by noting that the hp memristor defined by (5) and (6) on Page 81 of [11] is a trivial form of an Ideal Generic Memristor. In particular, let us rewrite (6) in [11] as follow.

$$\begin{eqnarray*}&&\frac{{\rm d}w}{{\rm d}t}=Ki,\end{eqnarray*}$$

where, $K={{\mu }_{v}}\frac{{{R}_{ON}}}{D}\triangleq \hat{f}(w).$

Applying (14a) to the above expression, we obtain

$$\begin{eqnarray*}&&\int \left( \frac{1}{K} \right){\rm d}w=\int i{\rm d}t,\end{eqnarray*}$$

$$\begin{eqnarray*}&&w=Kq,\end{eqnarray*}$$

which is (7) in [11].

Since an Ideal Generic Memristor is mathematically equivalent to an Ideal Memristor, it follows that the Titanium Dioxide hp memristor presented in the seminal 2008 nature paper [11] is an Ideal Memristor.

Table 5 shows the Lissajoux figure in the i_K versus v_K plane of the potassium ion-channel memristor for nine different frequencies, as computed from the first-order memristor equations shown in figure 15(e). Observe that at dc (f = 0 Hz), the i_K versus v_K Lissajoux figure is a single-valued curve. As the excitation frequency f increases, a loop whose lobe area⁵ $A{{r}^{+}}$ ⩾ 0 in the first quadrant, and Ar⁻ ≦̸ 0 in the third quadrant emerged and increases in magnitude between f = 1 Hz and f = 50 Hz. Thereafter, the magnitude of both lobe areas decreases monotonically from f = 200 Hz to f = 3 KHz. At very high frequencies, the magnitude of both lobe areas decreases to zero, resulting in a straight line through the origin at f = 1 MHz.

Table 5.  Lobe area and orientation of the pinched hysteresis loops of the potassium ion-channel memristor for input voltage v_K(t) = Asin (2πft) with amplitude A = 50 mV.

To confirm the 'zero phase-shift' signature of memristors, the sinusoidal input voltage waveform (in red color) v_K(t) and the corresponding periodic current waveform i_K(t) (in blue color) are plotted on the same set of axes in figures 16(a)–(c) for three frequencies f = 10 Hz, 50 Hz, and 200 Hz, respectively. Observe that i_K(t) = 0 whenever v_K(t) = 0, as expected.

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Table 6 shows the Lissajoux figure in the i_Na versus v_Na plane of the Sodium ion-channel memristor for nine different frequencies, as computed from the second-order memristor equations shown in figure 15(f). Again, the i_Na versus v_Na Lissajoux figure at dc (f = 0 Hz) is a single-valued curve. As the frequency increases, a pinched hysteresis loop with magnitude of lobe area Ar⁺ in the first quadrant, and magnitude of lobe area Ar⁻ in the third quadrant emerged and increases from f = 1 Hz to f = 50 Hz. Beyond this frequency, the magnitude of both lobe area decreases monotonically until it collapses into a straight line through the origin at f = 1 MHz.

Table 6.  Lobe area and orientation of the pinched hysteresis loops of the sodium ion-channel memristor for input voltage v_Na (t) = Asin (2πft) with amplitude A = 120 mV.

Figure 17 shows the waveform pairs (v(t), i(t)) plotted on the same pair of axes at f = 50 Hz, 200 Hz, and 500 Hz. Again, we observe i_Na(t) = 0 whenever v_Na(t) = 0, thereby confirming that it too exhibits the memristor 'zero-phase-shift' signature.

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It is important to understand that the Pinched hysteresis loops associated with a particular memristor depend not only on the amplitude and frequency of the sinusoidal voltage waveform applied across the memristor, but also on the choice of the waveforms as well, as clearly demonstrated as a function of frequency, and at dc (not sinusoidal), in table 5 for the potassium ion-channel memristors, and table 6 for the sodium ion-channel memristor. In other words, pinched hysteresis loops are not models because 'models must predict' [37, 38], and pinched hysteresis loops can not predict what happens if another waveform is applied across the device.

But pinched hysteresis loops measured from a device certifies that device is a memristor. Whether it is an Extended Memristor, a Generic Memristor, an Ideal Generic Memristor, or an Ideal Memristor, can be easily tested by additional properties manifested by different classes of memristors to be presented in the following sections.

A fundamental property of pinched hysteresis loops measured from a particular memristor is that it is an 'identity card' of that device. Apply the same input voltage waveform and the same pinched hysteresis loop must emerge. As a futuristic application, imagine every person has a catalog of 'healthy' pinched hysteresis loops measured from his potassium and sodium ion channels, as well as several other life-depending voltage-gated ion channels, such as calcium and chloride ion channels [40]. Since such 'healthy' pinched hysteresis loop fingerprints will change shape when a person developed an ion-channel disease⁶ [40] later in life, such ion-channel disease could conceivably be detected just by comparing his latest measured pinched hysteresis loops with those retrieved from his healthy ion-channel data base.

As illustrated in table 5, the pinched hysteresis loops associated with the potassium ion-channel memristor degenerates to a straight line for frequencies f > 1 MHz. Similarly, table 6 shows the pinched hysteresis loops of the sodium ion-channel memristor also degenerates to a straight line for frequencies f > 1 MHz. Such unique phenomenon must emerge at sufficiently high frequencies for all Generic Memristors as proved in page 212 of [42]. The same method of proof can be used to prove that for Extended Memristors (where the memristance function $R({\bf x},i)$, or memductance function $G({\bf x},v)$, depend not only on the state variable ${\bf x}$, but also on the input current i or voltage v, respectively), their pinched hysteresis loops must degenerate to a single-valued V–I curve resembling those measured from nonlinear resistors [3]. Since this phenomenon can occur only if the memristor is an Extended Memristor, it can be used to determine whether a memristor is a Generic Memristor (with linear v–i relationship) or an Extended Memristor (with single-valued nonlinear v–i relationship) at high frequencies.

Another peculiar aspect of the limiting behavior of Generic Memristors at high frequencies is that the slope of the limiting straight lines is not constant, but changes with the amplitude A of the sinusoidal input voltage v(t) = A sin ωt, as illustrated in figure 18 for the potassium memristor defined in figure 15(e), and in figure 19 for the sodium memristor defined in figure 15(f).

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The potassium ion-channel memristor defined in figure 15(e) is an example of a Generic Memristor described by one state equation; namely,

$$\begin{eqnarray}&&{{i}_{{\rm K}}}={{G}_{{\rm K}}}(x){{v}_{{\rm K}}},\end{eqnarray} \tag{ 22 }$$

$$\begin{eqnarray}&&\frac{{\rm d}x}{{\rm d}t}=f(x,{{v}_{{\rm K}}}),\end{eqnarray} \tag{ 23 }$$

where we have changed the potassium ion channel 'gate activation' variable 'n' to the symbol 'x' used in this paper. Equating (23) to zero and solving for the dc equilibrium point as a function of the applied dc voltage v_K = V_K, we obtain [43]:

$$\begin{eqnarray}&&x=\hat{x}({{V}_{{\rm K}}}).\end{eqnarray} \tag{ 24 }$$

Substituting (24) for x in (22), we obtain the dc V_K–I_K curve shown in figure 20 for the potassium ion-channel memristor.

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The sodium ion-channel memristor defined in figure 15(f) is an example of a Generic Memristor described by two state equations; namely,

$$\begin{eqnarray}&&{{i}_{{\rm Na}}}={{G}_{{\rm Na}}}({{x}_{1}},{{x}_{2}}){{v}_{{\rm Na}}},\end{eqnarray} \tag{ 25 }$$

$$\begin{eqnarray}&&\frac{{\rm d}{{x}_{1}}}{{\rm d}t}={{f}_{1}}({{x}_{1}},{{x}_{2}},{{v}_{{\rm Na}}}),\end{eqnarray} \tag{ 26 }$$

$$\begin{eqnarray}&&\frac{{\rm d}{{x}_{2}}}{{\rm d}t}={{f}_{2}}({{x}_{1}},{{x}_{2}},{{v}_{{\rm Na}}}),\end{eqnarray} \tag{ 27 }$$

where we have changed the sodium ion channel 'gate activation' variable 'm' to the symbol 'x₁' and the 'gate inactivation' variable 'h' to the symbol 'x₂', respectively, to be consistent with our notations in this paper. Equating (26) and (27) to zero and solving for the dc equilibrium point as a function of the applied dc voltage v_Na = V_Na, we obtain [43]:

$$\begin{eqnarray}&&{{x}_{1}}={{\hat{x}}_{1}}({{V}_{{\rm Na}}}),\end{eqnarray} \tag{ 28 }$$

$$\begin{eqnarray}&&{{x}_{2}}={{\hat{x}}_{2}}({{V}_{{\rm Na}}}).\end{eqnarray} \tag{ 29 }$$

Substituting (28) and (29) for x₁ and x₂ in (25), we obtain the dc V_Na–I_Na curve shown in figure 21 for the sodium ion-channel memristor. Observe that at the dc steady state regime, the potassium ion-channel is equivalent to a nonlinear resistor described by the dc V_K–I_K curve shown in figure 20 [37]. Likewise, at dc steady state, the sodium ion-channel memristor is equivalent to a nonlinear resistor described by the dc V_Na–I_Na curve shown in figure 21.

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In other words, Generic Memristors, in general, behave just like a nonlinear resistor under the dc regime⁷ .

Consider the three-segment PWL q versus φ curve (along with its equation) of an Ideal Memristor as shown in figure 22(a). It's memductance $G(\varphi )=\frac{{\rm d}\hat{q}(\varphi )}{{\rm d}\varphi }$ is shown in figure 22(b). Suppose we connect a Battery with voltage of E volts across this memristor at t = 0. Assuming $\varphi (0)=0$, the voltage waveform v(t) and flux waveform $\varphi (t)$ are shown in figure 23(a) for E > 0, and in figure 23(b) for E < 0. Observe that in either case, $\varphi (t)$ never stops, but increases to +∞ if E > 0, and to −∞ if E < 0. Hence, in theory, an Ideal memristor is never in equilibrium when connected to a battery. However, since the last two segments of the q versus φ curve in figure 22 are straight lines, after a sufficiently long time interval for the flux $\varphi (t)$ to travel from $\varphi =0$ in figure 22(a) to the breakpoint located at $\varphi =1$, if E > 0 (resp., to the breakpoint located at $\varphi =-1$ if E < 0), the memristor is equivalent (at dc) to a ¼ Ω (4 Siemens) resistor if E > 0 (resp., 2 Ω resistor if E < 0). Consequently, one would measure the rectifier-like dc V–I curve shown in figure 23(c). In this case, the Ideal Memristor defined in figure 22 has indeed a dc V–I curve in the sense that given any dc voltage v = E, this V–I curve would predict the corresponding dc current i = I, in accordance with figure 23(c), namely⁹ ,

$$\begin{eqnarray}&&I=2.25\;E+1.75\;\;E\;\;\;{\rm sgn} \;\;\varphi (t),\end{eqnarray} \tag{ 30 }$$

for all t > T, where $T=\frac{1}{\left| E \right|}$ is the time it takes to move from $\varphi =0$ to $\varphi =1$ along the PWL q versus φ curve in figure 22(a).

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We end this subsection by commenting that if the φ versus q curve of an ideal memristor tends to a straight line with slope R₁ for large positive values of φ, and slope R₂ ≪⃒ R₁ for large negative values of φ, regardless of the shape of the q versus φ curve between the two extreme straight-lines, then we may say that it has a dc V–I curve, as shown in figure 24, provided we understand that in term of the state variable φ, the memristor is in reality never in a steady-state regime since $\frac{{\rm d}\varphi }{{\rm d}t}=E\ne 0$.

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Consider an Ideal Memristor defined by

$$\begin{eqnarray}&&q=\frac{1}{3}{{\varphi }^{3}}.\end{eqnarray} \tag{ 31 }$$

The memductance is given by

$$\begin{eqnarray}&&G(\varphi )={{\varphi }^{2}}.\end{eqnarray} \tag{ 32 }$$

Applying an E-Volt battery across this memristor as in figure 22, we obtain the same $\varphi (t)$ shown in figure 23(a) for E > 0 and figure 23(b) for E < 0. The current i(t) in this case is

$$\begin{eqnarray}\left. \begin{array}{lllllllllllllll} i(t) & = & G(\varphi (t))E={{E}^{3}}{{t}^{2}},\quad for\;E\gt 0 \\ {} & = & -\;{{\left| E \right|}^{3}}{{t}^{2}}\quad \quad \quad \quad \quad \;for\;E\lt 0 \\ \end{array} \right\}.\end{eqnarray} \tag{ 33 }$$

It follows from (33) that this Ideal Memristor never settles down to a dc current when connected to a battery of either polarity, and hence it does not have a dc V–I curve!

Observe that in practice, such an Ideal Memristor would burnt-out long before its current gets too large. The moral of this example is that one should never connect a battery directly across an Ideal Memristor characterized by a monotonically-increasing 'polynomial' q versus φ curve, because the memductance G(t) = E³ × t² would quickly lead to the destruction of the device. It follows therefore that a sufficiently large resistor should always be connected in series with the battery so that the maximum current would be limited to E/R in the event that the memristor tends to a short circuit, in the worst case, after some finite time.

From a rigorous circuit-theoretic perspective, an Ideal Memristor has a dc V–I curve consisting of only one point, namely, the origin (V, I) = (0, 0)¹⁰ . This may look weird but it is correct. It also makes sense because no matter how small a dc voltage source, or dc current source, that one applies across an ideal memristor, it's associated flux, or charge is a ramp signal heading for infinity, and the memristor will never be at rest, and hence no other point in the V–I plane of an Ideal Memristor will ever be at a dc steady state.

The above memristive Nullator phenomenon is in fact the explanation for why one never sees from among the hundreds of papers published on memristors, a single dc V–I curve. It just does not exist¹¹ .

But this somewhat unexciting result is precisely the hallmark of an Ideal Memristor. If one fails to trace a dc V–I curve of a memristive device (i.e., a device endowed with pinched hysteresis loops in the v–i plane), because it keeps burning out, then that device is an Ideal Memristor!

Consider applying a sinusoidal voltage v(t) = 0.8 sin t across an Ideal Memristor with the three segment PWL q versus φ curve shown in figure 26. Assuming an initial flux $\varphi (0)=-0.4$ and using the analytical formula (34), we obtain the corresponding charge q(t) and current i(t), as well as, the memductance G(t), shown as vertically-aligned waveforms in the left column of figure 26. The loci corresponding to $\varphi (t)$ starts from the initial point and move along the leftmost blue line segment until it reaches the first breakpoint at $\varphi (0)=-0.25$, where it changes slope and moves upward along route , passing the origin, and continue its upward motion along route , until it arrives at the second breakpoint at $\varphi (0)=0.25$, whereupon it turns but continues moving rightward along route where the corresponding voltage v(t) reaches approximately its peak. Observe, however, $\varphi (t)$ must continue to increase until point at $t=\pi$, where it begins its return journey, along the same route . Somewhere around the midpoint of route , the loci crosses over the origin in the v–i plane, but still travelling leftward until it returns to point (relabelled as point ), and continues its return trip downward along route , (relabeled as route ). Eventually, it will arrive at point (relabelled as ), and continues its leftward odyssey until it returns to the starting point φ(0) = −0.4, at t = 2π.

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The pinched hysteresis loop associated with the above odyssey can be easily constructed as shown in the red loci on top of the right column in figure 26. Observe that the four abrupt jumps in i(t) occur at the four time instants where one of the two breakpoints and is crossed. Observe also the slope of the lowermost and uppermost loci is equal to the slope of the middle segment (resp., ) of the q versus φ curve. Observe also the slope of the near-horizontal line in the red v–i curve is equal to the slope of the leftmost (resp., rightmost) segment of the q versus φ curve.

Consider next a variant of tour 1 where the only change is the initial state, namely, from $\varphi (0)=-0.4$ to $\varphi (0)=-0.3$. The resulting tour map in figure 27 is virtually identical, except for the two double-arrowhead tails that stick out at the extremities. This new feature is important because many published pinched hysteresis loops exhibited similar tails [47].

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Our next tour is a slight variant of tour 2 where we only increase the initial state from $\varphi (0)=-{\mkern 1mu} 0.3$ to $\varphi (0)=-{\mkern 1mu} 0.25,$ a further tiny increase in $\varphi (0)$ of only 0.05. The resulting pinched hysteresis loop is shown in figure 28. Observe the dramatic change in the shape of the pinched hysteresis loop from a trapezoidal lobe to a triangular lobe! Such triangular-lobe features can also be found in many published papers [47, 48]. We can not overemphasize that the same memristive device can exhibit drastically different pinched hysteresis loops with the same applied input voltage by tuning only the initial state.

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Notice that all of the pinched hysteresis loops we have observed from the same Ideal Memristor in figures 26– 28 are odd symmetric, as expected from all Ideal memristors. Just in case the reader may attribute this odd symmetry property as resulting from the odd symmetry of both the excitation waveform v = A sin t, and that of the q versus φ curve, our final tour changes this odd-symmetric constitutive relation to the non-symmetric q versus φ curve in figure 29. The resulting pinched hysteresis loop is seen to retain its odd-symmetry property, as expected of all Ideal Memristors [62].

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In the semiconductor device parlance, a 'non-volatile' analog memory means a memory device that can store a continuous range of resistance values, and in which the stored data is preserved even after the electrical power is switched off from the system where the memory device is embedded. This class of memory devices is distinct from conventional non-volatile 'binary' memories where only the '0' state and '1' state can be stored. The main applications of non-volatile analog memories are for mimicking 'synapses' whose weight can be continuously tuned for 'learning' in intelligent brain-like machines [35].

Since the state equation defining an Ideal Memristor is

$$\begin{eqnarray*}&&\frac{{\rm d}\varphi }{{\rm d}t}=v,\end{eqnarray*}$$

for voltage-controlled Ideal memristors, and

$$\begin{eqnarray*}&&\frac{{\rm d}q}{{\rm d}t}=i,\end{eqnarray*}$$

for current-controlled Ideal memristors, switching off the power means setting both the memristor voltage v, and the memristor current i, to zero. In both cases,

$$\begin{eqnarray*}\begin{array}{lllllllllllllll} \varphi (t) & = & \varphi (0),\quad {\rm for}\;{\rm all}\;t\gt 0 \\ q(t) & = & q(0),\quad {\rm for}\;{\rm all}\;t\gt 0 \\ \end{array},\end{eqnarray*}$$

where $\varphi (0)$ and $q(0)$ are 'any' real number that $\varphi (t)$ and $q(t)$ assumes at $t={{0}^{-}}$, assuming the power is switched off at t = 0.

It follows that an Ideal Memristor is endowed with the capability to store any real number R,

$$\begin{eqnarray*}&&0\lt R\lt \infty \end{eqnarray*}$$

(in the form of a resistance, or a conductance), and retaining it for eternity without a power supply, at least in principle.

Since not all memristors are non-volatile memories, we end this section by calling attention to this very special virtue of an ideal memristor and its siblings:

We end this section by tuning the three parameters of a three-segment PWL q versus φ curve to obtain an Ideal Memristor that exhibit virtually the same well-known Bow-Tie shape pinched hysteresis loop presented in [14]. The red horizontal segment in the lower left column of figure 30(a) is most likely an artifact of an artificially imposed 'Compliance current' from the measuring instrument. For pedagogical reasons, the waveforms $\varphi (t)$, $q(t)$ and i(t) are presented in figure 31, along with the triangular-lobe pinched hysteresis loop.

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We wish to point out that there is a qualitative difference between Beck's pinched hysteresis loop in figure 30(a) and that predicted from the ideal memristor q versus φ curve in figure 30(c), namely, the v–i curve switches from a high-resistance state (the near-horizontal branch) to a low-resistance state at approximately v = −0.5 V, before the sinusoidal input switching signal had reached its most negative value. This discrepancy (assuming Beck's pinched hysteresis loop in figure 30(a) represents true real-time measurements and not an artifact of the measuring instrument) suggests that a generic or even an extended memristor may be needed to emulate Beck's pinched hysteresis loop more accurately.

When v = 0, the state equation reduces to

$$\begin{eqnarray}&&\frac{{\rm d}x}{{\rm d}t}=f(x),\end{eqnarray} \tag{ 37 }$$

which is best analyzed in the $\frac{{\rm d}x}{{\rm d}t}$ versus x plane shown in figure 32, where the vertical axis represents the rate of change $\frac{{\rm d}x}{{\rm d}t}$ of the state variable x. Observe that $\frac{{\rm d}x}{{\rm d}t}\gt 0$ at any point on the curve that lies above the x-axis. This means that the motion through each point on f(x) above the x-axis must move to the right as time increases, as depicted by three arrowheads pointing to the right. Similarly, since $\frac{{\rm d}x}{{\rm d}t}{\mkern 1mu} \lt {\mkern 1mu} 0$ below the x-axis, any point on f(x) lying below the x-axis must move to the left as time increases, as depicted by the three arrowheads pointing to the left.

Observe that at the three points , and where f(x) = 0, $\frac{{\rm d}x}{{\rm d}t}=0$. This means that if the initial state is located at one of these three points, there will be no motion at all. This is why , and are called an equilibrium point of this memristor when v = 0 (power is switched off).

A cursory inspection of the f(x) and the arrowheads indicating the direction of motion near each of the three equilibrium points shows that is an unstable equilibrium, and hence any initial state different from the three equilibrium points must move either to if x(0) < 30, or if x(0) > 30. In the theory of nonlinear dynamics [3, 49], the equilibrium point is said to be an attractor with a basin of attraction consisting of the open interval x < 30 because any initial point x(0) lying within this interval is attracted to . Similarly, the equilibrium point is said to be an attractor with a basin of attraction consisting of the open interval x > 30. In the parlance of nonlinear circuit theory, any curve f(x) plotted in the $\frac{{\rm d}x}{{\rm d}t}$ versus x plane, along with arrowheads pointing the direction of motion from representative points, is called a dynamic route [3, 45]. In spite of its simplicity, the dynamic route is the most powerful and useful tool for analyzing the dynamics of any first-order differential equation $\frac{{\rm d}x}{{\rm d}t}=f(x)$ because one can predict how any initial state will evolve with increasing time. For example, the dynamic route (for v = 0) in figure 32 implies that this memristor must assume one of two possible stable states and with the power switched off. This means that this memristor is a non-volatile (because v = 0) 'binary memory', whose small-signal conductance measured in a small neighborhood of each asymptotically stable [3, 45] equilibrium point Q defines the slope of a straight line through the origin (v = 0) whose equation is precisely Ohm's law. Since this memristor has two asymptotically stable equilibrium points and , the two corresponding memductances are given by

The above trivial calculations are summarized by two crossing straight lines with slope G₀ and G₁, respectively, in figure 32. It is traditional to call state the off state '0' because it is associated with a significantly higher resistance (or equivalently, smaller conductance). Similarly, the state is called the on state '1' because it is associated with a significantly lower resistance.

Our next task is to find a way to set the memristor by switching from a high-resistance state to its low resistance state . Conversely, we must also find a way to reset the memristor by switching from a low resistance state to a high resistance state .

The conceptually simplest way to switch (i.e., set) from the high-resistance (low conductance) state to the low resistance (high conductance) state is to apply a square pulse of appropriate pulse width Δt, and pulse amplitude A, as shown in the upper part of figure 33. An application of a 15 V square pulse is equivalent to translating f(x) upwards by 15 units, as shown by the . The dynamic route starting from at t = 0⁻ would jump abruptly from to a point directly above on the at t = 0⁺. Since the is located above the x-axis over the range of interest, its motion can only move to the right, until time t = Δt, where the square pulse returns to zero, and the reverts back abruptly to the , where upon the dynamics must continue to move along the dynamic route indicated by the two black arrowheads, until it converges to the low-resistance memory state .

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Switching back (i.e., reset) from the low-resistance (high conductance) state to the high-resistance (low conductance) state consists of simply applying a negative voltage pulse, as shown in the lower part of figure 33.

The top part of figure 34 shows the dynamic route resulting from a too-short pulse width Δt. Observe the return downward jump falls on the negative side of the , whose dynamic route demands that motion must move to the left, eventually returning to . Hence the switching process had failed in this case. It is clear from the upper diagram that to switch from to successfully, the pulse width Δt must be at least long enough for the downward jump to land to the right of the unstable equilibrium point , as in figure 33 (top).

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The lower part of figure 34 shows the dynamic route resulting from a too-small pulse amplitude A. Observe the return downward jump will fall on the negative side of the , where the dynamic route decreed that the motion must be to the left, thereby returning to the initial point . Observe that this scenario will take place no matter how large the pulse width is because it would take an infinite amount of time for the motion along the to reach x = 15 because the point at x = 15 (see inset) is a new equilibrium point while the square pulse is on, and it would take an infinite amount of time to arrive at an equilibrium point [3, 49]. For a successful switching from to , the pulse amplitude A must be at least equal to 10 in order for the minima of the to stay above x-axis, as in figure 33 (top).

Consider the Generic current-controlled memristor defined in figure 35, where the seven-segment PWL function f(x) for the memristor state equation shown in the bottom has an explicit formula (see appendix) shown on top. To focus on the dynamic nature of the non-volatile memory exhibited by this memristor, we had deliberately left the memristance R(x) unspecified to emphasize that, R(x) is irrelevant to the characterization of the memristor's non-volatility. The dynamic route at the bottom of figure 35 shows that this memristor is endowed with two disconnected closed intervals of stable (but not asymptotically stable) equilibrium points; namely x $\in$ [−2, −1] on the left of the origin, and x $\in$ [1, 2] on the right. Every point belonging to either interval is a member of an entire continuum of non-volatile memory states because $\frac{{\rm d}x}{{\rm d}t}=0$ for i = 0, and for any x belonging to either intervals where f(x) = 0. Observe that in contrast to ideal memristors where the entire x-axis is a non-volatile memory state, here we have two closed intervals of memory states. Which of the two intervals should be assigned an 'off' state, or an 'on' state, depends on how we define the memristance function R(x). It follows from the above analysis that the continuum non-volatility property of a memristor depends only on the closed interval of x where f(x) = 0, when i = I = 0.

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We have proved in section 5 that the pinched hysteresis loop of any Ideal Memristor, or its Ideal Generic Siblings, must necessarily be odd-symmetric for a sinusoidal input voltage or current. The four pinched hysteresis loops shown in figures 36(a)–(d) for the Generic Memristor defined in (35)-(36) and figure 32 (for four different values of the amplitude A) show that they are not symmetric. To analyze the source of the non-symmetry, figures 37 and 38 show the waveforms of v(t), i(t) and G(t), aligned vertically in time. A careful analysis and comparison with corresponding waveforms associated with Ideal Memristors reveals that whereas both the voltage v(t) and current i(t) of Ideal Memristors exhibit a reflected half-wave symmetry where the negative of the waveform during the second-half period of v(t) are mirror images of each other (See the left column of figures 26– 29, and 31), those shown in figures 37 and 38 do not exhibit such reflected half-wave symmetry. It follows that whenever a pinched hysteresis loop measured from a memristive device is not odd-symmetric then that device can not be an Ideal Memristor.

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Figure 43 shows a simple two-memristor circuit made of a battery and two voltage-controlled Generic memristors called PTC (positive temperature coefficient) thermistor and NTC (negative temperature coefficient) thermistor, respectively. The PTC thermistor is defined by:

where ${{\delta }_{P}}$, ${{H}_{CP}}$ and ${{T}_{OP}}$ are device parameters. It follows from (44) that the PTC thermistor is a 1st- order Generic Memristor with state variable ${{x}_{1}}={{T}_{PTC}}$, where ${{T}_{PTC}}$ denotes the body temperature of the PTC thermistor. Its dc V–I curve is shown in the inset of figure 43(a). The negative slope in this dc V–I curve implies the PTC thermistor is a locally active Generic memristor with the memductance given by

$$\begin{eqnarray}&&G({{x}_{1}})={{\left( {{R}_{0P}}{{e}^{{{\beta }_{P}}\left( {{x}_{1}}-{{T}_{0P}} \right)}} \right)}^{-1}}.\end{eqnarray} \tag{ 45 }$$

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The NTC thermistor is defined by:

where,

$$\begin{eqnarray*}&&G({{x}_{2}})={{\left( {{R}_{0N}}{{e}^{{{\beta }_{N}}\left( \frac{1}{{{x}_{2}}}-\frac{1}{{{T}_{0N}}} \right)}} \right)}^{-1}},\end{eqnarray*}$$

and ${{\delta }_{N}}$, ${{\beta }_{N}}$, ${{H}_{CN}}$, ${{R}_{ON}}$ and ${{T}_{ON}}$ are device parameters. It follows from (46) that the NTC thermistor is a 1st- order Generic Memristor with ${{x}_{2}}={{T}_{NTC}}$, where ${{T}_{NTC}}$ denotes the body temperature of the NTC memristor.

When a battery is connected across the two-memristor circuit in figure 43(a), a computer simulation of the two differential equations [50] gives the periodic waveform V_P (t) of the PTC thermistor voltage shown in figure 43(b), and the periodic waveform V_N(t) of the NTC thermistor voltage shown in figure 43(c). The experimental set-up for figure 43(a) was first demonstrated by Reenstra [50] where he had shown the first electronic circuit that oscillates without using an inductor, a capacitor, or a transistor. Here we identify the PTC thermistor to be the locally-active memristor which is responsible for achieving the oscillation without using any energy-storage elements, or other locally-active devices.

Consider the locally-active current-controlled Generic Memristor defined by

The electronic circuit realization¹⁴ in figure 44(a) (inside the red black box) is made of off-the-shelf electronic circuit components [51]. Since the memristance $R(x)=1.5({{x}^{2}}-1)$ shown in figure 44(b) is negative for $-1\lt x\lt 1$, this memristor is locally active, meaning that it can never be built without an internal power supply, such as a solar cell (with a small sunlight-seeking window), radioactive cell, or just a battery. The dc V–I curve of this memristor can be easily derived by setting $\frac{{\rm d}x}{{\rm d}t}$ in the memristor state equation (47b) in figure 45(a) to zero, and solving for x as a function of i; namely,

$$\begin{eqnarray}&&x=\frac{i}{i+0.6}.\end{eqnarray} \tag{ 48 }$$

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Substituting (48) for x in (47a), we obtain the following explicit equation for the dc V–I curve of this memristor:

$$\begin{eqnarray}&&V=-1.5\left[ 1-\frac{{{I}^{2}}}{{{(I+0.6)}^{2}}} \right]I.\end{eqnarray} \tag{ 49 }$$

The dc V–I curve measured from the red black box in figure 44(a) is shown in figure 44(c). Again, the local activity accolate bestowed upon this memristor implies that it requires a dc power supply.

When the locally-active Generic memristor is connected in series with an inductor (L = 3) and a capacitor (C = 1), as shown in figure 45(a), we observe a chaotic voltage waveform v_C (t) across the capacitor and a chaotic current waveform i_L (t) in the inductor, as shown in the top and bottom part of figure 45(b), respectively.

A projection of i_L (t) = i_C (t) versus the projection of v_C (t) in figure 45(c) shows a strange attractor [52] whose waveforms are not periodic but chaotic oscillations. Another chaotic voltage waveform of v_C(t) is shown in figure 45(d) (top) along with its fast Fourier transform confirming that the electrical power corresponding to v_C(t) is distributed over a continuous range of frequencies, which is the hallmark of chaotic systems.

Figure 46 shows a very simple circuit made of a battery in series with a resistor and a memristor defined earlier in figure 15(f), namely, the Hodgkin–Huxley sodium ion channel memristor, defined by two differential equations involving two state variables m and h, which we reproduce in figure 46(c) for the reader's convenience. A truncated version of the dc V–I curve of this 2nd-order Generic memristor (shown earlier in figure 21) is shown in figure 46(b). A numerical simulation of the circuit in figure 46(a) reveals the existence of an unstable limit cycle in the m versus h plane, as shown in figure 46(d), along with the periodic waveforms of m(t) and h(t).

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Observe that since the series combination of a memristor with a linear resistor is equivalent to another memristor [2], we can replace the resistor R and the Na memristor in figure 46(a) by a single composite 2nd-order memristor defined by the following composite state-depenndent

Ohm's law:

$$\begin{eqnarray}&&{{v}_{{\rm Na}}}=\left( R+\frac{1}{{{G}_{{\rm Na}}}(m,\ \;h)} \right)\;\;{{i}_{{\rm Na}}}.\end{eqnarray} \tag{ 50 }$$

This example represents nature's simplest possible oscillator where an oscillation is generated upon connecting a dc battery across a single two-terminal circuit element defined by the above state-dependent Ohm's law, and a state equation with two state variables m and h, defined in figure 46(c). It can be shown that this oscillation is generated via a sub critical Hopf bifurcation mechanism [59].