Low-complexity bit-parallel systolic architectures for computing A(x)B2(x) over GF(2m)

C.-Y. Lee; C.W. Chiou; A.-W. Deng; J.-M. Lin

Low-complexity bit-parallel systolic architectures for computing A(x)B²(x) over GF(2^m)

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Low-complexity bit-parallel systolic architectures for computing A(x)B²(x) over GF(2^m)

Author(s): C.-Y. Lee ; C.W. Chiou ; A.-W. Deng ; J.-M. Lin
DOI: 10.1049/ip-cds:20050188

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Author(s): C.-Y. Lee ¹ ; C.W. Chiou ² ; A.-W. Deng ³ ; J.-M. Lin ⁴
- Affiliations: 1: Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taiwan, Republic of China
  2: Department of Computer Science and Information Engineering, Ching Yun University, Chung-Li, Republic of China
  3: Department of Information Management, Ching Yun University, Chung-Li, Republic of China
  4: Department of Information Engineering and Computer Science, Feng Chia University, Taiwan, Republic of China
Source: Volume 153, Issue 4, August 2006, p. 399 – 406
DOI: 10.1049/ip-cds:20050188 , Print ISSN 1350-2409, Online ISSN 1359-7000

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Cryptographic applications based on finite fields have recently attracted considerable interest. This work develops two new algorithms, called the time-dependent and time-independent multiplication algorithms, for computing A(x)B²(x) over a finite field GF(2^m) using an interleaved conventional multiplication approach. The proposed algorithms allow efficient realisation of the bit-parallel multiplication using iterative arrays. The results reveal that our proposed time-dependent and time-independent multipliers save approximately 34% and 62% less space complexity, respectively, compared to the traditional multipliers for a general polynomial basis of GF(2^m). Additionally, the presented multiplication algorithms can also be effective Montgomery multiplication algorithms to yield low-complexity architectures.

References

1. 1)
  - C.Y. Lee . Low-complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials. IEE Proc., Comput. Digit. Tech. , 1 , 39 - 42
2. 2)
  - I.S. Reed , T.K. Truong . The use of finite fields to compute convolutions. IEEE Trans. Inf. Theory , 2 , 208 - 213
3. 3)
  - K. Parhi . (1999) VLSI signal processing systems: design and implementation.
4. 4)
  - B. Benjauthrit , I.S. Reed . Galois switching functions and their applications. IEEE Trans. Comput. , 78 - 86
5. 5)
  - Seroussi, G.: `Table of low-weight binary irreducible polynomials', HPL-98-135, Technical Report, Aug. 1998, Available at http://www.hpl.hp.com/techreports/98/HPL-98-135.html.
6. 6)
  - C. Lee , J. Horng , I. Jou , E. Lu . Low-complexity bit parallel systolic Montgomery multipliers for special classes of GF(2m). Trans. Comput. , 9 , 1061 - 1070
7. 7)
  - C.K. Koc , T. Acar . Montgomery multiplication in GF(2k). Des., Codes Cryptog. , 1 , 57 - 69
8. 8)
  - B.B. Zhou . A new bit-serial systolic multiplier over GF(2m). IEEE Trans. Comput. , 6 , 749 - 751
9. 9)
  - C.L. Wang , J.L. Lin . Systolic array implementation of multipliers for GF(2m). IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 796 - 800
10. 10)
  - C.S. Yeh , S. Reed , T.K. Truong . Systolic multipliers for finite fields GF(2m). IEEE Trans. Comput. , 357 - 360
11. 11)
  - C.Y. Lee . Low-latency bit-parallel systolic multiplier for irreducible xm+xn+1 with gcd(m,n)=1. IEICE Trans. Fundam. , 11 , 2844 - 2852
12. 12)
  - R.J. Baker . (2004) CMOS-circuit, design, layout, and simulation.
13. 13)
  - C.Y. Lee , C.W. Chiou , J.M. Lin . Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m). J. Electron. Test Theory Appl. , 5 , 539 - 549
14. 14)
  - S.Y. Kung . (1988) VLSI array processors.
15. 15)
  - R. Lidl , H. Niederreiter . (1994) Introduction to finite fields and their applications.
16. 16)
  - C.W. Chiou , C.Y. Lee . Multiplexer-based double-exponentiation for normal basis of GF(2m). Comput. Secur. , 1 , 83 - 86
17. 17)
  - C.Y. Lee . K-bit-parallel systolic multiplier and squarer over GF(2m). WSEAS Trans. Comput. , 1 , 1 - 7
18. 18)
  - S.W. Wei . A systolic power-sum circuit For GF(2m). IEEE Trans. Comput. , 2 , 226 - 229
19. 19)
  - F.J. MacWilliams , N.J.A. Sloane . (1977) The theory of error-correcting codes.
20. 20)
  - C.Y. Lee , E.H. Lu , J.Y. Lee . Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally-spaced polynomials. IEEE Trans. Comput. , 5 , 385 - 393
21. 21)
  - C.Y. Lee , C.W. Chiou . Design of low-complexity bit-parallel systolic Hankel multipliers to implement multiplication in normal and dual bases of GF(2m). IEICE Trans. Fundam. , 11 , 3169 - 3179
22. 22)
  - C.Y. Lee , E.H. Lu , L.F. Sun . Low-complexity bit-parallel systolic architecture for computing AB2+C in a class of finite field GF(2m). IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 519 - 523
23. 23)
  - C.L. Wang , J.H. Guo . New systolic arrays for AB2+C, inversion, and division in GF(2m). IEEE Trans. Comput. , 10 , 1120 - 1125
24. 24)
  - N.Y. Kim , H.S. Kim , K.Y. Yoo . Computation of AB2 multiplication in GF(2m) using low-complexity systolic architecture. IEE Proc., Circuits Devices Syst. , 2 , 119 - 123
25. 25)
  - S.M. Kang , Y. Leblebici . (1999) CMOS digital integrated circuits-analysis and design.
26. 26)
  - K.Z. Pekmestzi . Multiplexer-based array multipliers. IEEE Trans. Comput. , 1 , 15 - 23
27. 27)
  - S.T.J. Fenn , M. Benaissa , D. Taylor . Dual basis systolic multipliers for GF(2m). IEE Proc., Comput. Digit. Tech. , 1 , 43 - 46
28. 28)
  - C.C. Wang , D. Pei . A VLSI design for computing exponentiation in GF(2m) and its application to generate pseudorandom number sequences. IEEE Trans. Comput. , 2 , 258 - 262

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Low-complexity bit-parallel systolic architectures for computing A(x)B²(x) over GF(2^m)

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