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Reconfigurable baseband processing architecture for communication

Reconfigurable baseband processing architecture for communication

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Published

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

Inspec keywords: FIR filters; digital signal processing chips; software tools; reconfigurable architectures; performance evaluation; fast Fourier transforms

Other keywords: algorithm mapping; finite impulse response filter; high-level language; hardware generation; baseband signal processing; system performance evaluation; hardware resource usage; communication standards; software tools; multicore architectures; homogeneous control mechanism; reconfigurable baseband processing architecture; heterogeneous reconfigurable execution units; fast Fourier transform; digital signal processor chips

Subjects: Integral transforms; Performance evaluation and testing; Microprocessors and microcomputers; Digital signal processing; Filtering methods in signal processing; Integral transforms; Digital signal processing chips; Computer architecture

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