Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Scan chain configuration based X-filling for low power and high quality testing

Scan chain configuration based X-filling for low power and high quality testing

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

  • Author(s): Z. Chen 1 ; J. Feng 2 ; D. Xiang 3 ; B. Yin 3
    • View affiliations
    • Affiliations: 1: Department of Computer Science and Technology, Tsinghua University, Beijing, People's Republic of China
      2: Department of Microelectronics, Peking University, Beijing, People's Republic of China
      3: School of Software, Tsinghua University, Beijing, People's Republic of China
  • Source: Volume 4, Issue 1, January 2010, p. 1 – 13
    DOI:  10.1049/iet-cdt.2008.0163 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Published

Test power is a serious problem in the scan-based testing. DFT-based techniques and X-filling are two effective ways to reduce both shift power and capture power. However, few of the previous methods pay attention to the defect coverage when reducing the test power. Many of them, especially for X-filling methods, may lead to low defect coverage. In this paper, based on an effective scan chain configuration, we present a segment-based X-filling to reduce test power and keep the defect coverage. The scan chain configuration tries to cluster the scan flip-flops with common successors into one scan chain, in order to distribute the specified bits per pattern over a minimum number of chains. Based on the configuration, all the bits to some scan chains in a vector may be don't care(X). For these scan chains, segment-based X-filling is used to reduce test power and keep the defect coverage. Compared with the ordinary full-scan architecture, experimental results show that low test power and high defect coverage can be achieved.

Inspec keywords: design for testability; boundary scan testing; low-power electronics; flip-flops

Other keywords: shift power; scan flip-flops; X-filling; low power testing; high quality testing; scan chain configuration; capture power; DFT; scan-based testing

Subjects: Logic circuits; Logic and switching circuits; Logic design methods; Automatic test systems; Digital circuit design, modelling and testing

References

    1. 1)
      • McCluskey, E.J., Li, E., Tseng, C.W.: `Stuck-at fault versus actual defects', Proc. International Test Conf., 2000, p. 336–344.
    2. 2)
      • X. Chen , M.S. Hsiao . An overlapping scan architecture for reducing both test time and test power by pipelining fault detection. IEEE Trans. VLSI Syst. , 4 , 404 - 413
    3. 3)
      • A. Chandra , K. Chakrabarty . Low-power scan testing and test data compression for systems-on-a-chip. IEEE Trans. Comput. Aided Design , 5 , 597 - 604
    4. 4)
      • Cho, K.Y., Mitra, S., McCluskey, E.J.: `California scan architecture for high quanlity and low power testing', Proc. of IEEE Int. Test Conf., 2007, paper 25.3.
    5. 5)
      • Butler, K.M.: `Minimizing power consumption in scan testing: pattern generation and DFT techniques', Proc. IEEE Int. Test Conf., 2004, p. 355–364.
    6. 6)
      • N. Badereddine , Z. Wang , P. Girard . A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test , 4 , 353 - 364
    7. 7)
      • Astro: Advanced place-and-route solution for SoC design, Synopsys, http://www.synopsys.com/products/astro/astro.html.
    8. 8)
      • Sankaralingam, R., Oruganti, R.R., Touba, N.A.: `Static compaction techniques to control scan vector power dissipation', Proc. IEEE VLSI Test Symp., 2000, p. 35–40.
    9. 9)
      • J. Chen , C. Yang , K.J. Lee . Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. , 3 , 363 - 370
    10. 10)
      • A. Chandra , K. Chakrabarty . System-on-a-chip test data compression and decompression architectures based on Golomb codes. IEEE Trans. Comput. Aided Design , 355 - 368
    11. 11)
      • Sinanoglu, O., Orailoglu, A.: `A novel scan architecture for power efficient, rapid test', Proc. Int. Conf. Comput. Aided Des., 2002, p. 299–303.
    12. 12)
    13. 13)
      • Bonhomme, Y., Girard, P., Guiller, L., Landrault, C., Pravossoudovitch, S.: `A gated clock scheme for low power scan testing of logic IC's or embedded cores', Proc. IEEE Asian Test Symp, November 2001, p. 253–258.
    14. 14)
      • Baik, D., Saluja, K., Kajihara, S.: `Random access scan: a solution to test power, test data volume and test time', Proc. Int. Conf. VLSI Des, 2004, p. 883–888.
    15. 15)
      • Li, J., Xu, Q., Hu, Y., Li, X.: `iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing', Proc. Design Automation and Test in Europe, 2008, p. 1184–1190.
    16. 16)
      • Wen, X., Yamashitam, Y., Kajihara, S., Wang, L.T., Saluja, K.K., Kinoshita, K.: `On low-capture-power test generation for scan testing', Proc. of IEEE VLSI Test Symp., 2005, p. 265–270.
    17. 17)
      • Elm, M., Wunderlich, H.J., Imhof, M.E., Zoellin, C.G., Leenstra, J., Maeding, N.: `Scan chain clustering for test power reduction', Proc. Design Automation Conf., 2008, p. 828–833.
    18. 18)
      • Sankaralingam, R., Touba, N.A.: `Controlling peak power during scan testing', Proc. IEEE VLSI Test Symp., 2002, p. 153–159.
    19. 19)
      • D. Xiang , K. Li , J. Sun , H. Fujiwara . Reconfigured scan forest for test application cost, test data volume and test power reduction. IEEE Trans. Comput. , 4 , 557 - 562
    20. 20)
      • Wen, X., Kajihara, S., Miyase, K.: `A new ATPG method for efficient capture power reduction during scan testing', Proc. IEEE VLSI Test Symp., 2006, p. 58–65.
    21. 21)
      • V. Dabholkar , S. Chakravarty , I. Pomeranz , S. Reddy . Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput.-Aided Design , 1325 - 1333
    22. 22)
      • Ma, S.C., Franco, P., McCluskey, E.J.: `An experimental chip to evaluate test techniques experiment results', Proc. Int. Test Conf., 1995, p. 663–672.
    23. 23)
      • A. Al-Yamani , N. Devta-Prasanna , E. Chmelar , M. Grinchuk , A. Gunda . Scan test cost and power reduction through systematic scan reconfiguration. IEEE Trans. Comput. Aided Design , 5 , 907 - 918
    24. 24)
      • M. Bushnell , V.D. Agrawal . (2000) Essentials of electronic testing.
    25. 25)
      • Chandra, A., Kapur, R.: `Bounded adjacent fill for low capture power scan testing', Proc. IEEE VLSI Test Symp., 2008, p. 131–138.
    26. 26)
      • Miyase, K., Terashima, K., Kajihara, S., Wen, X., Reddy, S.M.: `On improving defect coverage of stuck-at fault tests', Proc. Asian Test Symp., 2005, p. 216–223.
    27. 27)
      • Remersaro, S., Lin, X., Zhang, Z., Reddy, S.M., Pomeranz, I., Rajski, J.: `Preferred fill: a scalable method to reduce capture power for scan based designs', Proc. IEEE Int. Test Conf., 2006, 32.2.
    28. 28)
      • P. Rosinger , B.M. Al-Hashimi , N. Nicolici . Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction. IEEE Trans. Comput. Aided Design , 7 , 1142 - 1153
    29. 29)
      • Bhattacharya, B.B., Seth, S.C., Zhang, S.: `Double-tree scan: a novel low-power scan-path architecture', Proc. Int. Test Conf., 2003, p. 470–479.
    30. 30)
      • Wang, Z., Chakrabarty, K.: `An efficient test pattern selection method for improving defect coverage with reduced test data volume and test application time', Proc. Asian Test Symp., 2006, p. 333–338.
    31. 31)
      • Saxena, J., Butler, K.M., Whetsel, L.: `An analysis of power reduction techniques in scan testing', Proc. IEEE Int. Test Conf., 2001, p. 670–677.
    32. 32)
      • Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.: `Glitch-aware pattern generation and optimization framework for power-safe scan test', Proc. IEEE VLSI Test Symp., 2007, p. 167–172.
    33. 33)
      • Chen, Z., Yin, B., Xiang, D.: `Conflict driven scan chain configuration for high transition fault coverage and low power', Proc. IEEE/ACM Asian and South Pacific Design Automation Conf., 2009, p. 666–671.
    34. 34)
      • Xu, Q., Hu, D., Xiang, D.: `Pattern-directed circuit virtual partitioning for test power reduction', Proc. IEEE Int. Test Conf., October 2007.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2008.0163
Loading

Related content

content/journals/10.1049/iet-cdt.2008.0163
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address