Simultaneous capture and shift power reduction test pattern generator for scan testing
Simultaneous capture and shift power reduction test pattern generator for scan testing
- Author(s): H.-T. Lin and J.C.-M. Li
- DOI: 10.1049/iet-cdt:20070088
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- Author(s): H.-T. Lin 1 and J.C.-M. Li 1
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View affiliations
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Affiliations:
1: Laboratory of Dependable Systems (LaDS), Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, Republic of China
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Affiliations:
1: Laboratory of Dependable Systems (LaDS), Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, Republic of China
- Source:
Volume 2, Issue 2,
March 2008,
p.
132 – 141
DOI: 10.1049/iet-cdt:20070088 , Print ISSN 1751-8601, Online ISSN 1751-861X
An automatic test pattern generation (ATPG) technique, which simultaneously reduces capture and shift power during scan testing, is presented. This ATPG performs power reduction during dynamic test compaction so the test length overhead is very small. This low-power test generator implements several novel techniques, such as parity backtrace, confined propagation, dynamic controllability and post-fill test regeneration. The experimental data on ISCAS benchmark circuits show that the peak capture power and the peak shift power are reduced by 31% and 26%, respectively.
Inspec keywords: circuit testing; automatic test pattern generation; controllability
Other keywords:
Subjects: Digital circuit design, modelling and testing; Automatic test systems
References
-
-
1)
- Wen, X., Kajihara, S., Miyase, K.: `A new ATPG method for efficient capture power reduction during scan testing', Proc. IEEE 24th VLSI Test Symp., 2006.
-
2)
- Girard, P., LandRault, C., Pravossoudovitch, S.: `Reducing power consumption during test application by test vector ordering', Proc. Int. Symp. Circuits and Systems (ISCAS 98), Part II, 1998, p. 296–299.
-
3)
- Huang, Y., Cheng, W.-T., Reddy, S.M.: `Statistical diagnosis for intermittent scan chain hold-time fault', Proc. IEEE Int. Test Conf., 2003, p. 319–327.
-
4)
- Corno, F., Rebaudengo, M., Reorda, M.S., Squillero, G.: `Low power BIST via non-linear hybrid cellular automata', IEEE Proc. VLSI Test Symp., 30 April–4 May 2000, p. 29–34.
-
5)
- Remersaro, S., Lin, X., Zhang, Z.: `Preferred fill: a scalable method to reduce capture power for scan based designs', Proc. IEEE Int. Test Conf., 2006.
-
6)
- P. Girard . Survey of low-power testing of VLSI circuits. IEEE Des. Test Comput. , 3 , 80 - 90
-
7)
- P.M. Rosinger , B.M. Al-Hashimi . Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction. IEEE Trans. Comput.-Aided Des. , 7 , 1142 - 1153
-
8)
- R.V. Dabholkar , S. Chakravarty , I. Pomeranz . Techniques for reducing power dissipation during test application in full scan circuits. IEEE Trans. Comput.-Aided Des. , 12 , 1325 - 1333
-
9)
- L.-T. Wang , C.-W. Wu , X. Wen . (2006) VLSI test principles and architectures: design for testability.
-
10)
- S. Wang , S.K. Gupta . ATPG for heat dissipation minimization during test application. IEEE Trans. Comput. , 2 , 256 - 262
-
11)
- Wen, X., Yamashita, Y., Kajihara, S.: `On low-capture-power test generation for scan testing', Proc. IEEE 23th VLSI Test Symp., 2005.
-
12)
- Sankaralingam, R., Touba, N.A.: `Controlling peak power during scan testing', Proc. IEEE 20th VLSI Test Symp., 2002, p. 319–324.
-
13)
- Kajihara, S., Ishida, K., Miyase, K.: `Test vector modification for power reduction during scan testing', Proc. IEEE 20th VLSI Test Symp., 2002.
-
14)
- Li, W., Reddy, S.M., Pomeranz, I.: `On reducing peak current and power during test', Proc. IEEE Symp. VLSI, 2005, p. 156–161.
-
15)
- Goldstein, L.H., Thigpen, E.L.: `SCOAP: Sandia controllability/observability analysis program', Proc. Des. Automation Conf., 1980, p. 190–196.
-
16)
- S. Wang , S.K. Gupta . An automatic test patten generator for minimizing switching activity during scan testing activity. IEEE Trans. Comput.-Aided Des. , 8 , 954 - 968
-
17)
- Butler, K.M., Jain, J.S.A., Jack Lewis, T.F.: `Minimizing power consumption in scan testing: pattern generation and DFT techniques', Proc. IEEE Int. Test Conf., 2004, p. 77–84.
-
18)
- Sankaralingam, R., Oruganti, R.R., Touba, N.A.: `Static compaction techniques to control scan vector power dissipation', Proc. IEEE 18th VLSI Test Symp., 2000, p. 319–324.
-
19)
- Remersaro, S., Lin, X., Zhang, Z.: `Low shift and capture power scan tests', Proc. Int. Conf. on VLSI Design, 2007, p. 793–798.
-
20)
- Wen, X., Yamashita, Y., Morishima, S.: `Low-capture-power test generation for scan-based at-speeding testing', Proc. IEEE Int. Test Conf., 2005.
-
21)
- P. Goel , B.C. Rosales . Dynamic test compaction with fault selection using “sensitizable” path tracing. IBM Tech. Disclosure Bull. , 5 , 1954 - 1958
-
1)
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