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Efficient modulo 2n+1 multipliers for diminished-1 representation

Efficient modulo 2n+1 multipliers for diminished-1 representation

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An efficient architecture for diminished-1 modulo (2n+1) multipliers is described. The new architecture is built using a pure radix-4 Booth recoding block, an inverted end-around-carry carry save adder tree and a final diminished-1 adder. Although one correction term is used, the complexity of the circuit is very simple. There are n/2 partial products (PP), one simple correction term and one constant, each one n bits wide. The new multipliers can handle zero inputs and results. The analytical and experimental results indicate that the new multipliers offer better speed and more compact than previously published solutions.

References

    1. 1)
      • Zimmermann, R.: `Efficient VLSI implementation of modulo (2', Proc. 14th IEEE Symp. Computer Arithmetic, April 1999, Adelaide, Australia, p. 158–167.
    2. 2)
      • O.L. MacSorley . High-speed arithmetic in binary computers. Proc. IRE , 67 - 91
    3. 3)
      • R. Conway , J. Nelson . Improved RNS FIR filter architectures. IEEE Trans. Circuits Syst. II, Exp. Briefs , 1 , 26 - 28
    4. 4)
      • C. Efstathiou , H.T. Vergos , D. Nikolos . Modified booth modulo 2n−1 multipliers. IEEE Trans. Comput. , 3 , 370 - 374
    5. 5)
      • L. Sousa , R. Chaves . A universal architecture for designing efficient modulo 2n+1 multipliers. IEEE Trans. Circuits Syst. I. , 6 , 1166 - 1178
    6. 6)
      • C. Efstathiou , H.T. Vergos , G. Dimitrakopoulos , D. Nikolos . Efficient diminished-1 modulo 2n+1 multipliers. IEEE Trans. Comput. , 4 , 491 - 496
    7. 7)
      • H.T. Vergos , C. Efstathiou , D. Nikolos . Diminished-one modulo 2n+1 adder design. IEEE Trans. Comput. , 12 , 1389 - 1399
    8. 8)
      • H.T. Vergos , C. Efstathiou . Design of efficient modulo 2n+1 multipliers. IET Comput. Digit. Tech. , 1 , 49 - 57
    9. 9)
      • Z. Wang , G.A. Jullien , W.C. Miller . An efficient tree architecture for modulo (2n+1) multiplication. J. VLSI Signal Process. , 241 - 248
    10. 10)
      • W. Chang , C. Jen . High-speed booth encoded parallel multiplier design. IEEE Trans. Comput. , 7 , 692 - 701
    11. 11)
      • A. Tyagi . A reduced-area scheme for carry-select adders. IEEE Trans. Comput. , 10 , 1163 - 1170
    12. 12)
      • A. Curiger , H. Bonnenberg , H. Kaeslin . Regular VLSI architectures for multiplication modulo (2n+1). IEEE J. Solid-State Circuits , 7 , 990 - 994
    13. 13)
      • Y. Ma . A simplified architecture for modulo (2n+1) multiplication. IEEE Trans. Comput. , 3 , 333 - 337
    14. 14)
      • C. Efstathiou , H.T. Vergos , D. Nikolos . Handling zero in diminished-one modulo 2n+1 adders. Int. J. Electron. , 2 , 133 - 144
    15. 15)
      • A. Hiassat . New memoryless mod (2n±1) residue multiplier. Electron. Lett. , 3 , 314 - 315
    16. 16)
      • L. Leibowitz . A simplified binary arithmetic for the Fermat number transform. IEEE Trans. Acoust. Speech Signal Process. , 356 - 359
    17. 17)
      • H.T. Vergos , C. Efstathiou . A unifying approach for weighted and diminished-1 modulo 2n+1 addition. IEEE Trans. Circuits Syst. II , 10 , 1041 - 1045
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