Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Low-power and high-quality Cordic-based Loeffler DCT for signal processing

Low-power and high-quality Cordic-based Loeffler DCT for signal processing

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

A computationally efficient and high-quality preserving discrete cosine transform (DCT) architecture is presented. It is obtained by optimising the Loeffler DCT based on the coordinate rotation digital computer (Cordic) algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e. similar to the complexity of the binDCT) without losing quality. After synthesising with TSMC 0.13-µm technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. The experimental results show that the proposed 8-point one-dimensional DCT architecture only consumes 19% of the area and about 16% of the power of the original Loeffler DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT. In this regard, the proposed Cordic-based Loeffler DCT is very suitable for low-power and high-quality encoder/decoders (codecs) used in battery-based systems.

Inspec keywords: signal processing; discrete cosine transforms; digital arithmetic; computational complexity

Other keywords: Cordic-based Loeffler DCT; coordinate rotation digital computer algorithm; signal processing; discrete cosine transform

Subjects: Digital arithmetic methods; Integral transforms; Integral transforms; Signal processing and detection; Digital signal processing

References

    1. 1)
      • S. Yu , E.E. Swartzlander . A scaled DCT architecture with the CORDIC algorithm. IEEE Trans. Signal Process. , 1 , 160 - 167
    2. 2)
      • Tran, T.D.: `A fast multiplierless block transform for image and video compression', Int. Conf. on Image Processing, 1999, p. 822–826.
    3. 3)
      • H. Jeong , J. Kim , W.K. Cho . Low-power multiplierless DCT architecture using image correlation. IEEE Trans. Consumer Electron. , 1 , 262 - 267
    4. 4)
      • Shams, A., Pan, W., Chidanandan, A., Bayoumi, M.A.: `A low power high performance distributed DCT architecture', IEEE Computer Society Annual Symp. on VLSI, 2002, p. 21–27.
    5. 5)
      • I.E.G. Richardson . (2002) Video codec design.
    6. 6)
      • R.C. Gonzales , R.E. Woods . (1993) Digital image processing.
    7. 7)
      • P. Rieder , J. Gotze , J.A. Nossek , C.S. Burrus . Parametrization of orthonormal wavelet transforms and their implementation. IEEE Trans. Circuits Syst II. , 2 , 217 - 226
    8. 8)
      • Duhamel, P., H'Mida, H.: `New 2n DCT algorithms suitable for VLSI implementation', IEEE Int. Conf. on ICASSP, 1987, 12, p. 1805–1808.
    9. 9)
      • Mariatos, E.P., Metafas, D.E., Hallas, J.A., Goutis, C.E.: `A fast DCT processor, based on special purpose CORDIC rotators', IEEE Int. Symp. on Circuits and Systems, 1994, 4, p. 271–274.
    10. 10)
      • P.P. Dang , P.M. Chau , T.Q. Nguyen , T.D. Tran . BinDCT and its efficent VLSI architectures for real-time embedded applications. J. Image Sci. Technol. , 2 , 124 - 137
    11. 11)
      • N.J. August , D.S. Ha . Low power design of DCT and IDCT for low bit rate video codecs. IEEE Trans. Multimedia , 3 , 414 - 422
    12. 12)
      • Kim, K., Beerel, P.A.: `A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform', IEEE Asia Pacific Conf. on ASICs, 1999, p. 135–138.
    13. 13)
      • Walther, J.S.: `A unified algorithm for elementary functions', Proc. Spring Joint Comput. Conf., 1971, 38, p. 379–385.
    14. 14)
      • Heyne, B., Bucker, M., Gotze, J.: `Implementation of a Cordic based FFT on a reconfigurable hardware accelerator', 3rdKarlsruhe Workshop on Software Radios, 2004.
    15. 15)
      • Park, J., Kwon, S., Roy, K.: `Low power reconfigurable DCT design based on sharing multiplication', IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, 2002, 3, p. III3116–III3119.
    16. 16)
      • W.H. Chen , C. Smith , S. Fralick . A fast computational algorithm for the discrete cosine transform. IEEE Trans. Commun. , 9 , 1004 - 1009
    17. 17)
      • K.K. Parhi , T. Nishitani . (1999) Digial signal processing for multimedia systems.
    18. 18)
      • Fanucci, L., Saponara, S.: `Data driven VLSI computation for low power DCT-based video coding', Int. Conf. on Electronics, Circuits and Systems, 2002, p. 541–544.
    19. 19)
      • Heyne, B., Gotze, J.: `A pure cordic based FFT for reconfigurable digital signal processing', 12thEuropean Signal Processing Conf., 2004.
    20. 20)
      • I.E.G. Richardson . (2003) H.264 and MPEG-4 video compression.
    21. 21)
      • The JPEG-6b website. http://www.ijg.org/, 1998.
    22. 22)
      • J.E. Volder . The CORDIC trigonometric computing technique. IRE Trans. Electron Comput. , 330 - 334
    23. 23)
      • The XVID Website. http://www.xvid.org/, 2005.
    24. 24)
      • Z. Wang . Fast algorithms for the discrete W transform and for the discrete Fourier transform. IEEE Trans. Acoust. Speech Signal Process. , 4 , 803 - 816
    25. 25)
      • J. Goetze , G. Hekstra . An algorithm and architecture based on orthonormal micro-rotations for computing the symmetric EVD. Integr. VLSI J. , 21 - 39
    26. 26)
      • S.F. Hsiao , Y.H. Hu , T.B. Juang , C.H. Lee . Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design. IEEE Trans. Circuits Syst. I , 8 , 1568 - 1579
    27. 27)
      • Loeffler, C., Lightenberg, A., Moschytz, G.S.: `Practical fast 1-D DCT algorithms with 11-multiplications', Proc. ICASSP, 1989, Glasgow, UK, 2, p. 988–991.
    28. 28)
      • J. Liang , T.D. Tran . Fast multiplierless approximations of the DCT with the lifting scheme. IEEE Trans. Signal Process. , 12 , 3032 - 3044
    29. 29)
      • C.C. Sung , S.J. Ruan , B.Y. Lin , M.C. Shie . Quality and power effcient architecture for the discrete cosine transform. IEICE Trans. Fundam. , 3500 - 3507
    30. 30)
      • Li, J., Lu, S.L.: `Low power design of two-dimensional DCT', IEEE Conf. on ASIC and Exhibit, 1996, p. 309–312.
    31. 31)
      • T.D. Tran . The binDCT: fast multiplierless approximation of the DCT. IEEE Signal Process. Lett. , 141 - 144
    32. 32)
      • T. Xanthopoulos , A.P. Chandrakasan . A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. IEEE J. Solid-State Circuits , 5 , 740 - 750
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20060289
Loading

Related content

content/journals/10.1049/iet-cds_20060289
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address