Hardware accelerators for CAD
Hardware accelerators for CAD
- Author(s): A.P. Ambler
- DOI: 10.1049/cae.1989.0020
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- Author(s): A.P. Ambler 1
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View affiliations
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Affiliations:
1: Department of Electrical Engineering and Electronics, Brunel University, Uxbridge, UK
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Affiliations:
1: Department of Electrical Engineering and Electronics, Brunel University, Uxbridge, UK
- Source:
Volume 6, Issue 3,
June 1989,
p.
77 – 81
DOI: 10.1049/cae.1989.0020 , Print ISSN 0263-9327, Online ISSN 2054-0353
© The Institution of Electrical Engineers
Published
The article describes what hardware accelerators are, what they can do, the way that they do it, possible limitations, possible alternatives, and some factors to be taken into account when considering the purchase of one of these machines.
Inspec keywords: circuit CAD
Other keywords:
Subjects: Computer-aided circuit analysis and design; Electronic engineering computing
References
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1)
- S.K. Jain , V.D. Agrawal . Statistical fault analysis. IEEE Des. Test Comput. , 3
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2)
- Deutsch, J.T., Newton, A.R.: `A multiprocessor implementation of relaxation-based electrical circuit simulation', ACM IEEE 21st Design Automation Conf., June 1984, Albuquerque, USA.
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3)
- Manning, R.L., Ambler, A.P.: `A relaxation-based algorithm for performing electrical level circuit simulation', Int. Workshop on Hardware Accelerators, September 1987, Oxford, England.
-
4)
- Microprocessor array speeds simulation. Electron. Week
-
5)
- Smith, L.T., Rezac, R.R.: `Methodology for and results from the use of a hardware logic simulation engine for fault simulation', IEEE Int. Test Conf., October 1984, Philadelphia, USA.
-
6)
- Coleman, N., Ambler, A.P.: `A multiprocessor for general VLSI design acceleration', Int. Workshop on Hardware Accelerators, September 1987, Oxford, England.
-
7)
- Seiler, L.D.: `A hardware assisted methodology for VLSI design rule checking', 1985, Ph.D. Thesis, Massachusetts Institute of Technology, USA.
-
8)
- A.P. Ambler , P. Agrawal , W. Moore . (1988) , Hardware accelerators for electrical CAD.
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9)
- J. Newkirk , A.P. Ambler , P. Agrawal , W. Moore . (1988) An introduction to CAE accelerators, Hardware accelerators for electrical CAD.
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10)
- Fourman, M.P.: `Verification using higher order specifications and transformations', Proc. Third Silicon Design Conf., July 1986, London, England.
-
11)
- Kane, R., Sahni, S.: `A systolic design-rule checker', ACM IEEE 21st Design Automation Conf., June 1984, Albuquerque, USA.
-
12)
- Kramer, G.A.: `Brute force and complexity management: two approaches to digital test generation', 1984, M.Sc. Thesis, Massachusetts Institute of Technology, USA.
-
13)
- T. Blank . A survey of hardware accelerators used in computer-aided design. IEEE Des. Test Comput. , 3
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14)
- Dally, W.J.: `The MOSSIM simulation engine architecture and design', 5123:TR" 84, Internal Report, 1984.
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1)
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