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CMOS current mode winner-take-all circuit with distributed hysteresis

CMOS current mode winner-take-all circuit with distributed hysteresis

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Published

An analogue-VLSI winner-take-all circuit is enhanced through the addition of hysteretic feedback that emphasises the spatial locality of competing signals using a resistive network. This circuit has applications to tasks in areas such as image processing, in which inputs are not stationary with respect to the circuit array.

Inspec keywords: real-time systems; computer vision; logic circuits; hysteresis; circuit feedback; focal planes; VLSI

Other keywords: distributed hysteresis; resistive network; image processing; spatial locality; hysteretic feedback; analogue-VLSI winner-take-all circuit; circuit array; CMOS current mode winner-take-all circuit

Subjects: Computer vision and image processing techniques; Logic circuits; Optical information, image and video signal processing; Pattern recognition; Logic and switching circuits; Image sensors

References

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      • C. Mead . (1989) Analog VLSI and neural systems.
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      • DeWeerth, S.P., Morris, T.G.: `Analog VLSI circuits for primitive sensory attention', Proc. IEEE Int. Symp. Circuits and Systems, 6, 6, p. 507–510.
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      • J.A. Starzyk , X. Fang . CMOS current mode winner-take-all circuit with both excitatory and inhibitoryfeedback. Electron. Lett. , 10 , 908 - 910
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      • Lazzaro, J., Ryckebusch, S., Mahowald, M.A., Mead, C.A.: `Winner-take-all networks of ', CS-TR-88-21, Technical report, 1989.
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