SCHEDULED MAINTENANCE
Realization of controllable graphene p–n junctions through gate dielectric engineering
Abstract
Graphene is considered to be one of the most promising materials in post-silicon electronics due to its remarkable geometric structure and physical properties. The realization of controllable and abrupt p–n junctions is crucial for the applications of graphene in nanoelectronics. In this paper, a novel step-dielectric design to modulate the doping profile in monolayer graphene is proposed and experimentally demonstrated. Resistance–voltage transfer characteristics of the fabricated device show the presence of two resistance peaks, verifying the formation of p–n junctions under certain bias conditions. Based on this technique, junctions with appreciable abruptness and controllability over the junction properties could be simultaneously obtained. In addition, mobility values of this device are extracted to be larger than 5000 cm2 V−1 s−1 due to the high quality of the gate oxide/graphene interfaces. This proposed technique would facilitate the development of novel devices composed of graphene p–n junctions.
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