Skip to main content
Log in

Synthesis of a Wireless Communication Analog Back-End Based on a Mismatch-Aware Symbolic Approach

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I & Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning.

The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations—symbol products and term sums—are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant.

A comparison between the presented synthesis technique and other purely numerical and numerical/symbolic approaches is also given.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. P. Rashinkar, P. Paterson, and L. Righ, System-on-a-Chip Verification, Methodology and Techniques. Kluwer Academic Publishers, 2001.

  2. J. Franca, N. Horta, M. Pereira, J. Vital, R. Castro-López, M. Delgado-Restituto, F.V. Fernández, A. Rodríguez-Vázquez, J. Ramos, and P. Santos, "RAPID—Retargetability for reusability of application-driven quadrature D/A interface block design." In Proc.of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, vol. 3, pp. 1679–1683.

    Google Scholar 

  3. G.G.E. Gielen and R.A. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits." In Proc.of the IEEE, 2000, vol. 88, no. 12, pp. 1825–1854.

    Google Scholar 

  4. T.S. Rappaport, Wireless Communications, Principles and Practice. Prentice Hall, 1996.

  5. K.R. Lakshmikumar, D.W. Green, K. Nagaraj, K.H. Lau, O.E. Agazzi, J.R. Barner, R.S. Shariatdoust, G.A. Wilson, T. Le, M.R. Dwarakanath, J.G. Ruch, J. Kumar, T. Ali-Vehmas, J.J. Junkkari, and L. Siren, "A baseband codec for digital cellular telephony." IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp. 1951–1958, 1991.

    Google Scholar 

  6. J.J.J. Haspeslagh, D. Sallaerts, P.P. Reusens, A. Vanwelsenaers, R. Granek, and D. Rabaey, "A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-held terminals." IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp. 1450–1457, 1990.

    Google Scholar 

  7. B. Baggini, L. Coppero, G. Gazzoli, L. Sforzini, F. Maloberti, and G. Palmisano, "An integrated circuit for GSM mobile communications." Analog Integrated Circuits and Signal Processing, vol. 2, no. 3, pp. 197–206, 1992.

    Google Scholar 

  8. P. Minogue, "A 3V GSM codec." IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1411–1420, 1995.

    Google Scholar 

  9. P.C. Maulik, N. van Bavel, K.S. Albright, and X.M. Gong, "An analog/digital interface for cellular telephony." IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 201–209, 1995.

    Google Scholar 

  10. V. Friedman, K.R. Lakshmikumar, D.L. Price, T.N. Le, and J. Kumar, "A baseband processor for IS-54 cellular telephony." IEEE Journal of Solid-State Circuits,vol. 31, no. 5, pp. 646–655, 1996.

    Google Scholar 

  11. H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A.L. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down Constraint Driven Methodology for Analog Integrated Circuits. Kluwer Academic Publishers, 1997.

  12. M.G.R. Degrauwe, O. Nys, E. Dijkstra, J. Rijmenants, S. Bitz, B.L. Goffart, E.A. Vittoz, S. Cserveny, C. Meixenberger, G. van der Stappen, and H.J.M. Oguey, "IDAC: An interactive design tool for analog CMOS circuits." IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 1106–1116, 1987.

    Google Scholar 

  13. R. Harjani, R.A. Rutenbar, and L.R. Carley, "OASYS: A framework for analog circuit synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 12, pp. 1247–1265, 1989.

    Google Scholar 

  14. H.Y. Koh, C.H. Sequin, and P.R. Gray, "OPASYN: A compiler for MOS operational amplifiers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 2, pp. 113–125, 1990.

    Google Scholar 

  15. G.G.E. Gielen, H.C.C. Walscharts, and W.M.C. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing." IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 707–713, 1989.

    Google Scholar 

  16. W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli, and A.L. Tits, "DELIGHT.SPICE: An optimization-based system for the design of integrated circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 4, pp. 501–519, 1988.

    Google Scholar 

  17. F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-Castro, J.L. Huertas, and A. Rodríguez-Vázquez, "Global design of analog cells using statistical optimization techniques." Analog Integrated Circuitsand Signal Processing, vol. 6, no. 3, pp. 179–195, 1994.

    Google Scholar 

  18. E. Ochotta, R.A. Rutenbar, and L.R. Carley, "Synthesis of high-performance analog circuits in ASTRX/OBLX." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 3, pp. 273–294, 1996.

    Google Scholar 

  19. R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, and J.R. Hellums, "Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 6, pp. 703–717, 2000.

    Google Scholar 

  20. R. Phelps, M.J. Krasnicki, R.A. Rutenbar, L.R. Carley, and J.R. Hellums, "A case study of synthesis for industrial-scale. analog IP: Redesign of the equalizer/filter frontend for an ADSL CODEC." In Proc.of the 37th ACM/IEEE Design Automation Conference, 2000, pp. 1–6.

  21. F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Kluwer Academic Publishers, 1999.

  22. M. Hershenson, S.P. Boyd, and T.H. Lee, "Optimal design of a CMOS op-amp via geometric programming."IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 1–21, 2001.

    Google Scholar 

  23. W. Kruiskamp and D. Leenaerts, "DARWIN: CMOS opamp synthesis by means of a genetic algorithm." In Proc.of the 32nd ACM/IEEE Design Automation Conference, 1995, pp. 433–438.

  24. W. Daems, W. Verhaegen, P. Wambacq, G.G.E. Gielen, and W.M.C. Sansen, "Evaluation of error-control strategies for the linear symbolic analysis of analog integrated circuits." IEEE Transactions on Circuits and Systems I, vol. 46, no. 5, pp. 594–606, 1999.

    Google Scholar 

  25. E. Hennig, Symbolic Approximation and Modeling Techniques for Analysis and Design of Analog Circuits, Ph.D. dissertation, Universität Kaiserlautern, Kaiserlautern, Germany, 2000.

    Google Scholar 

  26. Q. Yu and C. Sechen, "A unified approach to the approximate symbolic analysis of large analog integrated circuits." IEEE Transactions on Circuits and Systems I, vol. 43, no. 8, pp. 656–669, 1996.

    Google Scholar 

  27. O. Guerra, J.D. Rodríguez-García, E. Roca, F.V. Fernández, and A. Rodríguez-Vázquez, "A simplification before and during generation methodology for symbolic large-circuits analysis." In Proc.of the 5th IEEE InternationalConference on Electronic, Circuits and Systems, 1998, vol. 3, pp. 81–84.

    Google Scholar 

  28. O. Guerra, E. Roca, F.V. Fernández, and A. Rodríguez-Vázquez, "Approximate symbolic analysis of hierarchically decomposed analog circuits." Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp. 131–145, 2002.

    Google Scholar 

  29. G.G.E. Gielen, H.C.C. Walscharts, and W.M.C. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits." IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1587–1597, 1989.

    Google Scholar 

  30. F.V. Fernández, A. Rodríguez-Vázquez, and J.L. Huertas, "Interactive AC modelling and characterization of analog circuits via symbolic analysis." Analog Integrated Circuits and Signal Processing, vol. 1, no. 3, pp. 183–208, 1991.

    Google Scholar 

  31. S.J. Seda, M.G.R. Degrauwe, and W. Fichtner, "Lazy-expansion symbolic expression approximation in SYNAP." In Proc.of the IEEE/ACM International Conference on Computer-Aided Design, 1992, pp. 310–317.

  32. F.V. Fernández, A. Rodríguez-Vázquez, J.D. Martín, and J.L. Huertas, "Formula approximation for flat and hierarchical symbolic analysis." Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 43–58, 1993.

    Google Scholar 

  33. O. Guerra, J.D. Rodríguez-García, F.V. Fernández, and A. Rodríguez-Vázquez, "A symbolic pole/zero extraction methodology based on analysis of circuit time-constants." Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp. 101–118, 2002.

    Google Scholar 

  34. F.V. Fernández, O. Guerra, J.D. Rodríguez-García, and A. Rodríguez-Vázquez, "Symbolic analysis of analog integrated circuits: The numerical reference generation problem." IEEE Transactions on Circuits and Systems II, vol. 45, no. 10, pp. 1351–1361, 1998.

    Google Scholar 

  35. J.D. Rodríguez-García, O. Guerra, E. Roca, F.V. Fernández, and A. Rodríguez-Vázquez, "Error control insimplification before generation algorithms for symbolic analysis of large analogue circuits." Electronic Letters, vol. 35, no. 4, pp. 260–261, 1999.

    Google Scholar 

  36. O. Guerra, F.V. Fernández, and A. Rodríguez-Vázquez, "Approximate symbolic analysis of mismatch characteristics in analog circuits." In Proc.of the 7th International Workshop on Symbolic Methods and Applications to Circuit Design, 2002, pp. 5–8.

  37. R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro, and A. Rodríguez-Vázquez, "Generation of technology-portable flexible analog blocks." In Proc.of the 9th IEEE International Symposium on Circuits and Systems, 2002, vol. 2, pp. 61–64.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Castro-López, R., Guerra, O., Fernández, F. et al. Synthesis of a Wireless Communication Analog Back-End Based on a Mismatch-Aware Symbolic Approach. Analog Integrated Circuits and Signal Processing 40, 215–233 (2004). https://doi.org/10.1023/B:ALOG.0000034825.47829.04

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/B:ALOG.0000034825.47829.04

Navigation