Skip to main content
SpringerLink
Log in

Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range.

The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A. Moini, Vision Chips. Kluwer Academic Publishers, 2000.

  2. T. Roska and A. Rodríguez-Vázquez (Eds.), Towards the Visual Microprocessor. John Wiley & Sons, 2001.

  3. P. Kinget and M. Steyaert, “An analog parallel array processor for real-time sensor signal processing,” in Proc. of the IEEE International Solid-State Circuits Conference. San Francisco, CA, USA, Feb. 1996. pp. 92–93.

  4. R. Domínguez-Castro, S. Espejo, A. Rodríguez-Vázquez, R. Carmona, P. Foldesy, A. Zarándy, P. Szolgay, T. Sziranyi, and T. Roska, “A 0.8 µm CMOS programmable mixed-signal focal-plane array processor with on-chip binary imaging and instruction storage.” IEEE Journal of Solid State Circuits, vol. 32, no. 7. pp. 1013–1026, 1997.

    Google Scholar 

  5. A. Paasio, A. Dawidziuk, K. Halonen, and V. Porra, “Minimum size 0.5 µm CMOS programable 48 × 48 CNN test chip,” in Proc. of the 1997 European Conference on Circuit Theory and Design, Budapest, Hungary, Sept. 1997. pp. 154–156.

  6. G. Liñán, S. Espejo, R. Domínguez-Castro, and A. Rodríguez-Vázquez, “ACE4k:Ananalog I/O 64×64 visual microprocessor chip with 7-bit accuracy.” Int. Journal of Circuit Theory and Applications, vol. 30. pp. 89–116, March 2002.

    Google Scholar 

  7. G. Liñán, S. Espejo, R. Domínguez-Castro, and A. Rodríguez-Vázquez, “Architectural and basic circuit considerations for a flexible 128 × 128 mixed-signal SIMD vision chip.” Analog Integrated Circuits and Signal Processing, vol. 33, no. 2. pp. 179–190, Nov. 2002.

    Google Scholar 

  8. G. Liñán, “Design of low-power mixed signal visual microprocessors on chip.” Ph.D. dissertation, University of Seville, 2002.

  9. A. Rodríguez-Vázquez, R. Domínguez-Castro, and S. Espejo, “Design of CNN universal chips: Trends and obstacles,” in IEEE 1994 Int. Workshop on Cellular Neural Networks, ISBN 0-7803-2070-0, Rome: IEEE Press 1994. pp. 59–60.

    Google Scholar 

  10. P. Kinget and M. Steyaert, “Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits,” in Proc. Custom Integrated Conference, May 1996. pp. 333–336.

  11. B. Roska and F.S. Werblin, “Vertical interactions across ten parallel, stacked representations in the mammalian retina.” Nature, vol. 410. pp. 583–587, March 2001.

    Google Scholar 

  12. R. Domínguez-Castro, A. Rodríguez-Vázquez, S. Espejo, and R. Carmona, “Four-quadrant one-transistor synapse for high density CNN implementations,” in Proc. of the Fifth IEEE International Workshop on Cellular Neural Networks and their Applications, London, UK, April 1998. pp. 243–248.

  13. M.J.M. Pelgrom et al., “Matching properties of MOS transistors.” IEEE J. Solid-State Circuits, vol. 24. pp. 1433–1440, Oct. 1989.

    Google Scholar 

  14. E.A. Vittoz, “Future of analog VLSI in the VLSI environment,” in Proc. of ISCAS, 1990. pp. 1372–1390.

  15. C. Hu, “FutureCMOSscaling and reliability.” Proc. of the IEEE, vol. 81. pp. 682–689, 1993.

    Google Scholar 

  16. C. Mead, “Scaling ofMOStechnology to submicrometer feature sizes.” Analog Integrated Circuits and Signal Processing, vol. 6. pp. 9–25, 1994.

    Google Scholar 

  17. M. Steyaert et al., “Speed-power-accuracy trade off in high-speed analog-to-digital converters: Now and in the future,” in Proc. of the 9thWorkshop on Analog Circuit Design, April 2000.

Download references

Author information

Authors and Affiliations

  1. Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012, Sevilla, Spain

    A. Rodríguez-Vázquez, G. Liñán, S. Espejo & R. Domínguez-Castro

Authors
  1. A. Rodríguez-Vázquez
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. Liñán
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Espejo
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. R. Domínguez-Castro
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Rodríguez-Vázquez, A., Liñán, G., Espejo, S. et al. Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips. Analog Integrated Circuits and Signal Processing 37, 73–83 (2003). https://doi.org/10.1023/A:1025410523340

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1025410523340

Search

Navigation