Abstract
Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidanceof over-constrained synchronization, and its simplified clocking requirements.However, analysis and optimization of self-timed systems under real-time constraintsis challenging due to the complex, irregular dynamics of self-timed operation.In this paper, we review a number of high-level intermediate representationsfor compiling dataflow programs onto self-timed DSP platforms, including representationsfor modeling the placement of interprocessor communication (IPC) operations;separating synchronization from data transfer during IPC; modeling and optimizinglinear orderings of communication operations; performing accurate design spaceexploration under communication resource contention; and exploring alternativeprocessor assignments during the synthesis process. We review the structureof these representations, and discuss efficient techniques that operate onthem to streamline scheduling, communication synthesis, and power managementof multiprocessor DSP implementations.
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Back, T., U. Hammel, and H.-P. Schwefel. Evolutionary Computation: Comments on the History and Current State. IEEE Transactions on Evolutionary Computation, vol. 1, no.1 pp.3-17, April 1997.
Bambha, N. K., and S. S. Bhattacharyya. A Joint Power/Performance OptimizationTechnique for Multiprocessor Systems Using a Period Graph Construct. In Proceedings of the International Symposium on Systems Synthesis, pp. 91–97, Sept. 2000.
Bambha, N. K., S. S. Bhattacharyya, J. Teich, and E. Zitzler. Hybrid Search Strategies for DynamicVoltage Scaling in Embedded Multiprocessors. In Proceedings of the International Workshop on Hardware/Software Co-Design, pp. 243–248, Copenhagen, Denmark, April 2001.
Correa, R. C., A. Ferreira, and P. Rebreyend. Scheduling Multiprocessor Tasks with Genetic Algorithms. IEEE Transactions on Parallel and Distributed Systems, vol. 0, pp. 825–837, 1999.
Dasdan, A., and R. K. Gupta. Faster Maximum and Minimum Mean Cycle Algorithms for System-Performance Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 no.10 pp. 889–899, Oct. 1998.
Khandelia, M., and S. S. Bhattacharyya. Contention-Conscious Transaction Ordering in Embedded Multiprocessors. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, pp. 276–285, Boston, MA, July 2000.
Khandelia, M., and S. S. Bhattacharyya. Contention-Conscious Transaction Ordering in Embedded Multiprocessor Systems. Technical Report UMIACS-TR-2000-09, Institute for Advanced Computer Studies, University of Maryland at College Park, March 2000. Also Computer Science Technical Report CS-TR-4109.
Kianzad, V., and S. S. Bhattacharyya. Multiprocessor Clustering for Embedded Systems. In Proceedings of the European Conference on Parallel Computing, pp. 697–701, Manchester, United Kingdom, Aug. 2001.
Lee, E. A., and S. Ha. Scheduling Strategies for Multiprocessor Real Time DSP. In Proceedings of the Global Telecommunications Conference, Nov. 1989.
Lee, E. A., and D. G. Messerschmitt. Static Scheduling of Synchronous Dataflow Programs for Digital Signal Processing. IEEE Transactions on Computers, Feb. 1987.
Lieverse, P., E. F. Deprettere, A. C. J. Kienhuis, and E. A. DeKock. A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. Journal of VLSI Signal Processing, vol. 22, pp. 9–20, Aug. 1999.
Morse, J. N. Reducing the Size of the Nondominated Set: Pruning by Clustering. Computers and Operations Research, vol.7, no.1–2, pp. 55–66, 1980.
Peterson, J. L. Petri Net Theory and Modeling of Systems. Prentice-Hall Inc., Englewood Cliffs, NJ, 1981.
Reiter, R. Scheduling Parallel Computations. Journal of the Association for Computing Machinery, vol. 15, no.4, pp. 590–599, Oct. 1968.
Sarkar, V. Partitioning and Scheduling Parallel Programs for Multiprocessors. MIT Press, 1989.
Sih, G. C., and E. Lee. A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. IEEE Transactions on Parallel and Distributed Systems, vol. 4, no.2, 1993.
Sriram, S., and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, Inc., 2000.
Sriram, S., and E. A. Lee. Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. Journal of VLSI Signal Processing, March 1997.
Yang, T. and, A. Gerasoulis. DSC: Scheduling Parallel Tasks on an Unbounded Number of Processors. IEEE Transactions on Parallel and Distributed Systems, vol. 5, pp. 951–967, 1994.
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Bambha, N., Kianzad, V., Khandelia, M. et al. Intermediate Representations for Design Automation of Multiprocessor DSP Systems. Design Automation for Embedded Systems 7, 307–323 (2002). https://doi.org/10.1023/A:1020307222052
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DOI: https://doi.org/10.1023/A:1020307222052