Skip to main content
SpringerLink
Log in

Performance-Scalable Array Architectures for Modular Multiplication

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. R.L. Rivest, A. Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems,” Comm. ACM, vol. 21,no. 2, 1978, pp. 120-126.

    Article  MathSciNet  Google Scholar 

  2. S.Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.

    Google Scholar 

  3. P. Kornerup, “A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms,” IEEE Trans. Comput., vol. 43,no. 8, 1994, pp. 892-898.

    Article  MATH  Google Scholar 

  4. C.Y. Su, S.A. Hwang, P.S. Chen, and C.W. Wu, “An Improved Montgomery's Algorithm for High-Speed RSA Public-Key Cryptosystem,” IEEE Transactions on VLSI Syst., vol. 7,no. 2, 1999, pp.280-284.

    Article  Google Scholar 

  5. W.C. Tsai, C.B. Shung, and S.J. Wang, “Two Systolic Architectures for Modular Multiplication,” IEEE Trans. on VLSI Syst., vol. 8,no. 1, 2000, pp. 103-107.

    Article  Google Scholar 

  6. C.D. Walter, “Systolic Modular Multiplication,” IEEE Trans. Comput., vol. 42,no. 3, 1993, pp. 376-378.

    Article  Google Scholar 

  7. Y.J. Jeong and W.P. Burleson, “VLSI Array Algorithms and Architectures for RSA Modular Multiplication,” IEEE Trans. VLSI Syst., vol. 5,no. 2, 1997, pp. 211-217.

    Article  Google Scholar 

  8. J.H. Guo and C.L. Wang, “A Novel Digit-Serial Systolic Array for Modular Multiplication,” in Proc. of the 1998 IEEE Int. Symposium on Circuits and Syst., vol. 2, 1998, pp. 177-180.

    Google Scholar 

  9. N. Takagi, “A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation,” IEEE Trans. Comput, vol. 41,no. 8, 1992.

  10. C.D. Walter, “Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addtion,” IEEE Trans. Comput., vol. 46,no. 2, 1997.

  11. H. Orup, “Simplifying Quotient Determination in High-Radix Modular Multiplication,” in Proc. of the 12th Symp. on Computer Arithmetic, 1995, pp.193-199.

  12. G.R. Blakley, “A Computer Algorithm for Calculating the Product AB Modulo M,” IEEE Trans. Comput., vol. C-32,no. 5, 1983, pp. 497-500.

    Article  Google Scholar 

  13. P.L. Montgomery, “Modular Multiplication Without Trial Division,” Math. Comp., vol. 44,no. 170, 1985, pp. 519-521.

    Article  MathSciNet  MATH  Google Scholar 

  14. W.L. Freking and K.K. Parhi, “A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations,” in Proc. 1999 IEEE International Conference on Computer Design, 1999, pp. 80-87.

  15. A.F. Tenca and C.K. Koc, “A Scalable Architecture for Montgomery Multiplication,” Cryptographic Hardware and Embedded Systems, LNCS no. 1717, 1999, pp. 94-108.

  16. K.K. Parhi, “High-Level Algorithm and Architecture Transformations for DSP Synthesis,” Journal of VLSI Signal Processing, vol. 9,no. 1/2, 1995, pp. 121-143.

    Article  Google Scholar 

  17. J. Teich and L. Thiele, “Partitioning of Processor Arrays: A Piecewise Regular Approach,” INTEGRATION: The VLSI Journal, vol. 14,no. 3, 1993, pp. 297-332.

    MATH  Google Scholar 

  18. J. Teich, L. Thiele, and L. Zhang, “Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources,” in Proc. on Application-Specific Systems, Architectures, and Processors (ASAP '96), 1996, pp. 131-144.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. SE, Minneapolis, MN, 55455, USA

    William L. Freking & Keshab K. Parhi

Authors
  1. William L. Freking
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Keshab K. Parhi
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Freking, W.L., Parhi, K.K. Performance-Scalable Array Architectures for Modular Multiplication. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 31, 101–116 (2002). https://doi.org/10.1023/A:1015337204517

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1015337204517

Search

Navigation