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Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits

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Abstract

This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.

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Authors and Affiliations

  1. Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes s/n., E-41012, Sevilla, Spain

    O. Guerra, E. Roca, F. V. Fernández & A. Rodríguez-Vázquez

  2. Área de Electrónica, Escuela Superior de Ingenieros, Edificio Plaza de América, Isla de la Cartuja s/n., E-41092, Sevilla, Spain

    F. V. Fernández & A. Rodríguez-Vázquez

Authors
  1. O. Guerra
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  2. E. Roca
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  3. F. V. Fernández
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  4. A. Rodríguez-Vázquez
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Guerra, O., Roca, E., Fernández, F.V. et al. Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits. Analog Integrated Circuits and Signal Processing 31, 131–145 (2002). https://doi.org/10.1023/A:1015094011107

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