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Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec

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Abstract

Several parallel, pipelined and folded architectures with different throughput rates are presented for computation of DCT, one of the fundamental operations in image/video coding. This paper begins with a new decomposition algorithm for the 1-D DCT coefficient matrix. Then the 2-D DCT problem is converted into the corresponding 1-D counterpart through a regular index mapping technique. Afterward, depending on the trade-off between hardware complexity and speed performance, the derived decomposition algorithm is transformed into different parallel-pipelined and folded architectures that realize the butterfly operations and the post-processing operations. Compared to other DCT processor, our proposed parallel-pipelined architectures, without any intermediate transpose memory, have the features of modularity, regularity, locality, scalability, and pipelinability, with arithmetic hardware cost proportional to the logarithm of the transform length.

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  1. Institute of Computer and Information Engineering, National Sun Yat-Sen University, No. 70, Lien-Hai Road, Kaohsiung, 804, Taiwan, R.O.C

    Shen-Fu Hsiao & Jian-Ming Tseng

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  1. Shen-Fu Hsiao
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  2. Jian-Ming Tseng
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Hsiao, SF., Tseng, JM. Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 205–220 (2001). https://doi.org/10.1023/A:1011165524744

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  • DOI: https://doi.org/10.1023/A:1011165524744

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