Skip to main content
Log in

Oscillation Ring Delay Test for High Performance Microprocessors

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A.K. Pramanick and S.M. Reddy, “On the Detection of Delay Faults, ” Proc. of International Test Conference, 1988, pp. 845–856.

  2. V.S. Iyengar, B.K. Rosen, and I. Spillinger, “Delay Test Generation 1-Concepts and Coverage Metrics, ” Proc. of International Test Conference, 1988, pp. 857–866.

  3. V.S. Iyengar, B.K. Rosen, and J.A. Waicukauski, “On Computing the Sizes of Detected Delay Faults, ” IEEE Trans. On CAD-9, pp. 299–312, 1990.

  4. G.L. Smith, “Model for Delay Faults Based upon Paths, ” Proc. of International Test Conference, 1985, pp. 342–349.

  5. W.N. Lee, S.M. Reddy, and S.K. Sahni, “On Path Selection in Combinational Circuits, ” IEEE Trans. on CAD-8, pp. 56–63, 1989.

  6. S.M. Reddy, C.J. Lin, and S. Patil, “On Automatic Test Pattern Generation for the Detection of Path Delay Faults, ” Proc. of International Conference on Computer Aided Design, 1987, pp. 284–287.

  7. K.T. Cheng and H.C. Chen, “Classification and Identification of Nonrobust Untestable Path Delay Faults, ” IEEE Trans. on CAD-15, pp. 1027–1034, 1996.

  8. E.S. Park and M.R. Mercer, “Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit, ” Proc. of International Test Conference, 1987, pp. 1027–1034.

  9. M.C. Lin, J.E. Chen, and C.L. Lee, “TRANS: A Fast and Memory Efficient Path Delay Fault Simulator, ” Proc. of European Conference on Design Automation and Test, 1994, pp. 508–512.

  10. K. Fuchs, M. Pabst, and T. Rossel, “RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes, ” IEEE Trans. on CAD-13, pp. 1550–1562, 1994.

  11. J. Savir and W.H. McAnney, “Random Pattern Testability of Delay Fault, ” Proc. of International Test Conference, 1986, pp. 163–173.

  12. A.K. Pramanick and S.M. Reddy, “Sufficient Multiple Path Propagating Tests for Delay Faults, ” Journal of Electronic Testing: Theory and Applications, Vol. 7, pp. 157–167, 1995.

    Google Scholar 

  13. S. Kundu, S.M. Reddy, and N.K. Jha, “Design of Robustly Testable Combinational Circuits, ” IEEE Trans. on CAD-10, pp. 1036–1048, 1991.

  14. I. Pomeranz, S.M. Reddy, and P. Uppaluri, “EST: A Non-enumerative Test Generation Method for Path Delay Faults in Oscillation Ring Delay Test 155 Combinational Circuits, ” Proc. of International Conference on Design Automation, 1993, pp. 439–445.

  15. S.D. Lohit and H.R. Thomas, “Application of Ring Oscillators to Characterize Transmission Lines in VLSI Circuits, ” IEEE Trans on Component, Packaging, and Manufacturing Technologies, part-B, Vol. 18, pp. 651–657, 1995.

    Google Scholar 

  16. K. Kurita, T. Hotta, T. Nakano, and N. Kitamura, “PLL-Based BiCMOS on-Chip Clock Generator for Very High-Speed Microprocessor, ” IEEE JSSC-26, pp. 585–589, 1991.

  17. M. Kaneko and K. Sakaguchi, “Oscillation Fault Diagnosis for Analog Circuits Based on Boundary Search with Perturbation Model, ” IEEE Int. Symp. on Circuits and Systems, pp. 93–96, 1994.

  18. B. Razavi, “A Study of Phase Noise in CMOS Oscillators, ” IEEE JSSC-31, pp. 331–343, 1995.

  19. W.C. Wu, “Delay Testing and Fault Simulation for Digital Circuits, ” Ph.D. Thesis, Department of Electronics Engineering, National Chiao Tung University, June 1997.

  20. W.C. Wu, C.L. Lee, J.E. Chen, and M. Abadir, “Oscillation Ring Delay Test for High Performance Microprocessor, ” presented in 1st Int. Workshop on Microprocessor Test and Verification, 1998.

  21. K. Arabi and B. Kaminska, “Oscillation-Based Test Strategy for Analog and Mixed-Signal Integrated Circuits, ” Proc. of VLSI Test Symp., 1996.

  22. W.T. Cheng, “The BACK Algorithm for Sequential Test Generation, ” International Conference on Computer-Aided-Design, 1991, pp. 214–218.

  23. F. Berglez and H. Fujiwara, “Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN, ” Special Session on ATPG and Fault Simulation, IEEE Int. Symp. On Circuits and Systems, 1985.

  24. F. Berglez, D. Brglez, and K. Kozminski, “Combinational Pro-files of Sequential Benchmark Circuits, ” IEEE Int. Symp. On Circuits and Systems, pp. 1929–1934, 1989.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wu, W.C., Lee, C.L., Wu, M.S. et al. Oscillation Ring Delay Test for High Performance Microprocessors. Journal of Electronic Testing 16, 147–155 (2000). https://doi.org/10.1023/A:1008365428314

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008365428314

Navigation