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False-Path Removal Using Delay Fault Simulation

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Abstract

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.

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References

  1. M.A. Gharaybeh,V.D. Agrawal, and M.L. Bushnell, “False-Path Removal Using Delay Fault Simulation,” Proc. 7th IEEE Asian Test Symp., Dec. 1998, pp. 82-87.

  2. A. Krstić and K.-T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers, Boston, 1998.

    Google Scholar 

  3. M.A. Gharaybeh, M.L. Bushnell, and V.D. Agrawal, “Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests,” Proc. International Test Conf., Oct. 1995, pp. 139-148.

  4. S. Chakravarty, “A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits,” IEEE Trans. on Computers, Vol. 45, No. 8, pp. 985-991, Aug. 1996.

    Google Scholar 

  5. S. Devadas and K. Keutzer, “Synthesis of Robust Delay-Fault-Testable Circuits: Theory,” IEEE Trans. on CAD, Vol. 11, No. 1, pp. 87-101, Jan. 1992.

    Google Scholar 

  6. H. Hengster, R. Drechsler, and B. Becker, “On Local Transformation and Path Delay Fault Testability,” J. Electronic Testing: Theory and Applications, Vol. 7, No. 3, pp. 173-192, Dec. 1995.

    Google Scholar 

  7. N.K. Jha, I. Pomeranz, S.M. Reddy, and R.J. Miller, “Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability,” Proc. 22nd Fault-Tolerant Computing Symp., July 1992, pp. 280-287.

  8. W. Ke and P.R. Menon, “Synthesis of Delay-Verifiable Combinational Circuits,” IEEE Trans. on Computers, Vol. 44, No. 2, pp. 213-222, Feb. 1995.

    Google Scholar 

  9. A. Krstić and K.-T. Cheng, “Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability,” J. Electronic Testing: Theory and Applications, Vol. 11, No. 1, pp. 43-54, Aug. 1997.

    Google Scholar 

  10. S. Kundu, S.M. Reddy, and N.K. Jha, “Design of Robustly Testable Combinational Logic Circuits,” IEEE Trans. on CAD, Vol. 10, No. 8, pp. 1036-1048, Aug. 1991.

    Google Scholar 

  11. A.K. Pramanick and S.M. Reddy, “On the Design of Path Delay Fault Testable Combinational Circuits,” Proc. 19th Fault-Tolerant Computing Symp., June 1990, pp. 374-381.

  12. K. Heragu, J.H. Patel, and V.D. Agrawal, “Fast Identification of Untestable Delay Faults Using Implications,” Proc. International Conference on Computer-Aided Design, Nov. 1997, pp. 642-647.

  13. Z. Li, R. Brayton, and Y. Min, “Efficient Identification of Non-Robustly Untestable Path Delay Faults,” Proc. International Test Conference, Nov. 1997, pp. 992-997.

  14. A.K. Majhi, “Algorithms for Test Generation and Fault Simulation of Path-Delay Faults in Logic Circuits,” PhD Thesis, Electrical Communication Eng. Dept., Indian Institute of Science, Bangalore, 1996.

    Google Scholar 

  15. S. Majumder, V.D. Agrawal, and M.L. Bushnell, “On Delay-Untestable Paths and Stuck-Fault Redundancy,” Proc. 16th IEEE VLSI Test Symp., April 1998, pp. 194-199.

  16. A. Saldanha, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation,” Proc. 29th ACM/IEEE Design Automation Conference, June 1992, pp. 173-176.

  17. V.D. Agrawal, M.L. Bushnell, and Q. Lin, “Redundancy Identification using Transitive Closure,” Proc. 5th IEEE Asian Test Symp., Nov. 1996, pp. 4-9.

  18. M.A. Iyer and M. Abramovici, “Low-Cost Redundancy Identification for Combinational Circuits,” Proc. 7th International Conf. on VLSI Design, 1994, pp. 315-318.

  19. J.K. Zhao, E.M. Rudnick, and J.H. Patel, “Static Logic Implication with Application to Redundancy Identification,” Proc. 15th IEEE VLSI Test Symp., April 1997, pp. 288-293.

  20. M.A. Gharaybeh, M.L. Bushnell, and V.D. Agrawal, “The Path-Status Graph with Application to Delay Fault Simulation,” IEEE Trans. on CAD, Vol. 17, No. 4, pp. 324-332, April 1998. Also in Proc. IEEE International Test Conference, Oct. 1996, pp. 276-285.

    Google Scholar 

  21. E.J. McCluskey, “Transients in Combinational Logic Circuits,” Redundancy Techniques for Computing Systems, R.H. Wilcox and W.C. Mann (Eds.), Spartan Books, 1962, pp. 9-46.

  22. N.Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, Reading Massachusetts, 1985.

    Google Scholar 

  23. F. Brglez, D. Bryan, and K. Ko?mi?ski, “Combinational Profiles of Sequential Benchmark Circuits,” Proc. IEEE International Symp. on Circuits and Systems, May 1989, pp. 1929-1934.

  24. C. Parodi, V.D. Agrawal, M.L. Bushnell, and S. Wu, “A Non-Enumerative Path Delay Fault Simulator for Sequential Circuits,” Proc. International Test Conference, Oct. 1998, pp. 934-943.

  25. R. Bencivenga, T.J. Chakraborty, and S. Davidson, “GENTEST: The Architecture of Sequential Circuit Test Generator,” Proc. Custom Integrated Circuits Conference, May 1991, pp. 17.1.1-17.1.14.

  26. K. Keutzer, S. Malik, and A. Saldanha, “Is Redundancy Necessary to Reduce Delay?,” IEEE Trans. on CAD, Vol. 10, No. 4, pp. 427-435, April 1991.

    Google Scholar 

  27. A. Saldanha, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Circuit Structure Relations to Redundancy and Delay,” IEEE Trans. on CAD, Vol. 13, No. 7, pp. 875-883, July 1994.

    Google Scholar 

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Authors
  1. Marwan A. Gharaybeh
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  2. Vishwani D. Agrawal
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  3. Michael L. Bushnell
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  4. Carlos G. Parodi
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Gharaybeh, M.A., Agrawal, V.D., Bushnell, M.L. et al. False-Path Removal Using Delay Fault Simulation. Journal of Electronic Testing 16, 463–476 (2000). https://doi.org/10.1023/A:1008316631868

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