Skip to main content
SpringerLink
Log in

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing “design for reconfiguration” where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. G.R. Goslin, “A Guide to Using Field Programmable Gate Ar-rays (FPGAs) for Application-Specific Digital Signal Processing Performance, ” in Proceedings of the SPIE, High Speed Com-puting, Digital Signal Processing and Filtering using Reconfig-urable Logic, J. Schewel, P.M. Athanas, V.M. Bove, Jr., and J. Watson (Eds.), Boston, MA, Nov. 1996, pp. 321–331.

  2. J.D. Hadley and B. Hutchings, “Design Methodologies for Par-tially Reconfigured Systems, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1995, pp. 78–84.

  3. R. Woods, D. Trainor, and J.P. Heron, “Applying an XC6200 to Real-Time Image Processing, ” IEEE Design And Test of Computers, Special Edition on FPGAs, Jan.–Mar. 1998, pp. 30–38.

  4. C.F.N. Cowan, R.F. Woods, J.P. Heron, P. Power, and F.J. Sweeney, “Advances in Adaptive Signal Processing: Totally Adaptive Systems, ” in Proceedings of the IFAC Workshop on ACSP, University of Strathclyde, Aug. 1998, pp. 221–230.

  5. XC6200 FPGA Family Data Sheet, Xilinx Inc.1997.

  6. Atmel 40K Family Data Sheet, Atmel Inc. 1997.

  7. S.M. Scalera and J.R. Vazquez, “The Design and Implementation of a Context Switching FPGA, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1998, pp. 78–85.

  8. J. McHenry, P. Dowd, T. Carrozi, F. Pellegrino, and W. Cocks, “An FPGA-Based Coprocessor for ATMFirewalls, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1997, pp. 45–54.

  9. N. Shirazi, W. Luk, and P. Cheung, “Automating Production of Run-Time Reconfigurable Designs, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1998, pp. 147–156.

  10. S. Hauck, Z. Li, and E. Schwabe, “Configuration Compression for the Xilinx XC6200 FPGA, ” in Proceedings of the IEEE. Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1998, pp. 138–146.

  11. J.D. Hadley and B. Hutchings, “Design Methodologies for Par-tially Reconfigured Systems, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1995, pp. 78–84.

  12. J. Villasenor and W.H. Mangione-Smith, “Configurable Computing, ” Scientific America, June 1997, pp. 54–59.

  13. J. Burns, A. Donlin, J. Hogg, S. Singh, and M. de Wit, “A Dy-namic Reconfiguration Run-Time System, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1997, pp. 82–91.

  14. W. Luk, S. Guo, N. Shirazi, and N. Zhuang, “A Framework for Developing Parameterised FPGA Libraries, ” in Proceedings of the 6th Int'l Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science 1142, Darmstadt, Germany: Springer-Verlag, pp. 327–336.

  15. M. Wirthlin and B. Hutchings, “Improving Functional Density Using Run-Time Circuit Reconfiguration, ” IEEE Transactions on Very Large Scale Integration Systems, vol. 6, no.2, 1998, pp. 247–256.

    Article  Google Scholar 

  16. G. Brebner, “A Virtual Hardware Operating System for the Xilinx XC6200, ” in Proc.of the 6th Int'l Workshop on Field Pro-grammable Logic and Applications, Lecture Notes in Computer Science 1142, Darmstadt, Germany: Springer-Verlag, 1996, pp. 327–336.

  17. T. Kean, B. New, and B. Slous, “A Constant Coefficient Multiplier for the XC6200, ” in Proceedings of the 6th International Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science 1142, Darmstadt, Germany: Springer-Verlag, Sep. 1996, pp. 230–236.

  18. W. Luk, N. Shirazi, S. Guo, and P. Cheung, “Pipeline Morphing and Virtual Pipelines, ” in Proceedings of the 7th International Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science 1304, London, UK: Springer-Verlag, Sep. 1997, pp. 111–120.

  19. M. Rencher and B.L. Hutchings, “Automated Target Recognition on Splash 2, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1997, pp. 192–200.

  20. G. Brebner, “The Swappable Logic Unit: AParadigm for Virtual Hardware, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1997, pp. 95–104.

  21. W. Luk, N. Shirazi, and P. Cheung, “Compilation Tools for Run-Time Reconfigurable Designs, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1997, pp. 72–81.

  22. R. Hudson, D. Lehn, and P. Athanas, “A Run Time Reconfigurable Engine for Image Interpolation, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1998, pp. 88–95.

  23. S. Sezer, J. Heron, R. Woods, R. Turner, and A. Marshall, “Fast Partial Reconfiguration for FCCMs, ” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, USA, April 1998, pp. 318–319.

  24. J.P. Heron and R.F. Woods, “Architectural Strategies for Implementing an Image Processing Algorithm on XC6200 FPGA, ” in Proceedings of the 6th International Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science, R.W. Hartenstein and M. Glesner (Eds.), ISBN 3–540–61730–2, 1996, pp. 317–326.

  25. S. McQuillan and J.V. McCanny, “A VLSI Module for High Performance Multiplication, Division and Square Root, ” IEE Proceedings on Computers and Digital Techniques, Part E, vol. 136, no. 6, 1992, pp. 505–510.

    Article  Google Scholar 

  26. S.Y. Kung, “VLSI Array Processors, ” Englewood Cliffs, New Jersey: Prentice-Hall, 1988.

    Google Scholar 

  27. Virtex Configuration Architecture: Advanced Users' Guide, XAPP151, V1.0, Xilinx, April 9, 1999.

Download references

Author information

Authors and Affiliations

  1. School of Electrical and Electronic Engineering, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast, BT9 5AH, Northern Ireland

    J.P. Heron, R. Woods, S. Sezer & R.H. Turner

Authors
  1. J.P. Heron
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. R. Woods
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Sezer
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. R.H. Turner
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Heron, J., Woods, R., Sezer, S. et al. Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 97–113 (2001). https://doi.org/10.1023/A:1008115306599

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008115306599

Search

Navigation