Elsevier

Solid-State Electronics

Volume 132, June 2017, Pages 103-108
Solid-State Electronics

Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation

https://doi.org/10.1016/j.sse.2017.03.014Get rights and content

Highlights

  • Parasitic resistance and its variability are obstacles for the scaling of FinFETs.

  • Reducing the fin thickness degrades in parasitic resistance and its variability.

  • Implantation of As instead of P for the extension doping causes the same effect.

  • These phenomena are observed to be caused by residual defects in the crystalline fin.

Abstract

The influence of extension doping on parasitic resistance and its variability has been investigated for FinFETs. Electrical characterization of FinFETs and crystallinity evaluation of the doped fin structure are carried out for different fin thicknesses and different donor species for ion implantation, i.e., As and P. Reducing the fin thickness and the use of donor species with a larger mass cause serious degradation in the variability and median value of the parasitic resistance. Crystallinity evaluation by transmission electron microscope reveals that significant crystal defects remain after dopant activation annealing for the cases of smaller fin thickness and the implanted dopant with a larger mass. The unrecovered defects cause serious degradation in the parasitic resistance and its variability.

Introduction

FinFETs have been introduced to overcome the short channel effect (SCE) of MOSFETs and are used as a state-of-the-art CMOS platform from the generation of 22-nm technology [1]. The advantage of the FinFETs is that their double gate structure has better electrostatic control in the channel than the bulk-planar MOSFETs, and this results in effective suppression of the SCE [2], [3]. The SCE suppression can further be enhanced by reducing the fin thickness [4]. This strategy is implemented in the 14-nm technology [5] and realizes an improved on-current of the FinFETs maintaining a similar off-current in comparison to the previous technology node [1]. While reducing the fin thickness is required for proceeding with the technology node, it is also known that it can cause a serious increase in the parasitic resistance due to the difficulty in doping the fin structure by ion implantation [6], [7]. The increase in the parasitic resistance of the scaled fin thickness is understood to be because of the residual defects caused by the ion implantation [8], [9], [10]. The variability of the transistor characteristics is another obstacle of scaling [11], [12]. Though FinFETs with an undoped channel can suppress variability of the threshold voltage significantly [5], [13], it is predicted that the fluctuation in the parasitic resistance emerges as one of the dominant origins of the characteristics variability in the case of a gate length smaller than 20 nm [14]. Therefore, suppression of the variability in the parasitic resistance is a critical issue for conducting further scaling of the FinFET together with the suppression of the nominal parasitic resistance.

In this work, the impact of the extension doping conditions is investigated in detail by evaluating the parasitic resistance and its variability for FinFETs. The conditions used for the extension doping include the varying fin thicknesses and different donor species, i.e., As and P, implanted to the fin structure. In addition to the electrical characterization of the parasitic resistance and its variability, crystalline defects in the doped fin structure are evaluated to discuss the correlation between the residual defects and the parasitic resistance.

Section snippets

Sample preparation

N-channel FinFETs were fabricated for the electrical characterization of the parasitic resistance. The FinFET fabrication was carried out by a gate-first process flow shown in Fig. 1. Fin channels with (1 1 0)-oriented sidewalls were fabricated from a (1 0 0) silicon-on-insulator (SOI) wafer. The fin thickness (Tfin) was designed to be 20 or 30 nm for comparison. Gate stack formation was carried out by depositing TiN by sputtering on a 2.5-nm-thick SiO2 [15]. After gate patterning, ion implantation

Results and discussion

The fabricated n-type FinFETs with a single-fin channel and a designed gate length (Lg) of 100 nm was electrically characterized. Fig. 2 shows the drain current (Id) vs. gate voltage (Vg) characteristics of the 48 sample FinFETs with an identically designed dimension. Drain voltage was set at 50 mV, at which the on-resistance Ron of the FinFET is sensitive to the parasitic resistance Rpara. In the following analysis, Vt for each Id–Vg curve is defined using a constant-current criterion, namely, Vg

Summary

Decreasing the fin thickness and using As instead of P for extension doping of the FinFETs cause a significant increase in the parasitic resistance and its variability. TEM evaluation of the fin structure, which underwent the extension doping process, reveals a significant increase in the residual defects when a reduced fin thickness was used and when As was used. These results show that using P with a smaller atomic mass is preferable to conduct the scaling of FinFET dimensions suppressing the

Acknowledgement

This work was supported in part by a Grant-in-Aid for Scientific Research (No. 26289113) from the Japan Society for the Promotion of Science.

Takashi Matsukawa received the B.S., M.S., and Ph.D degrees in electrical engineering from School of Science and Engineering, Waseda University, Tokyo, Japan.

In 1998, he joined the Electrotechnical Laboratory, which is former organization of National Institute of Advanced Industrial Science and Technology (AIST). He has been working on development of front-end process technology, variability issues of the FinFETs and technologies for suppressing the variability. He is now a group leader of the

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  • Takashi Matsukawa received the B.S., M.S., and Ph.D degrees in electrical engineering from School of Science and Engineering, Waseda University, Tokyo, Japan.

    In 1998, he joined the Electrotechnical Laboratory, which is former organization of National Institute of Advanced Industrial Science and Technology (AIST). He has been working on development of front-end process technology, variability issues of the FinFETs and technologies for suppressing the variability. He is now a group leader of the AIST and leads the research on the silicon-based CMOS devices.

    He is a member of the IEEE Electron Devices Society, and the Japan Society of Applied Physics.

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