Effects of additional oxidation after Ge condensation on electrical properties of germanium-on-insulator p-channel MOSFETs

Abstract

This paper discusses the effects of additional oxidation after Ge condensation on electrical characteristics of fully depleted germanium-on-insulator (FDGOI) p-channel MOSFETs. We highlight the passivation of the back interface of GOI layers by the additional oxidation. Moreover, the electrical characteristics of the fabricated GOI pMOSFETs were systematically analyzed with varying the additional oxidation time and resulting compressive strain. It is found that 12-nm-thick GOI pMOSFETs with 0.94 % compressive strain were realized without any additional oxidation by utilizing strained silicon-on-insulator (sSOI), showing the drive current over twice as high as that of unstrained Ge pMOSFETs. However, the devices exhibit large positive threshold voltage (V_th) shifts, large subthreshold swing (SS), and high off-state current (I_off), attributable to the poor MOS interfaces with buried oxides (BOX). This back channel MOS interface can be effectively passivated without significant growth of the BOX thickness by additional oxidation, leading to the restoration of the V_th shifts, improved SS, and dramatic reduction of I_off. It is also found that the improvement of the back interface (Ge/BOX) and the strain relaxation occur simultaneously by the additional oxidation, which is corroborated by Raman spectroscopy, transmission electron microscopy (TEM), and the electrical characterization of GOI pMOSFETs. As a result, a possible physical model to explain the observed phenomena was proposed.

Introduction

Large scale integrated circuits (LSIs) have been driven mainly by dimension scaling with the advent of the Moore’s law as guided in [1]. However, performance gain in sub-100 nm regime has diminished due to high external resistance and more importantly, source injection velocity of Si [2], [3], [4], [5], [6], [7], [8], presenting a plethora of challenges to continue the historic progress. To circumvent the challenges in boosting device performance, various technology knobs such as strained Si, SiGe channels, high-k/metal-gate, extremely thin silicon on insulator (ETSOI) and multi-gate structures have been implemented from the 90 nm technology node. Among a variety of the technology boosters, utilizing channel materials with high mobility and resultant high injection velocity is a very attractive option at low power supply voltage [9], [10], [11].

Germanium is one of the most promising channel materials for complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs), in particular, pMOSFETs, because of its inherently superior hole mobility and light hole effective mass [12], [13], [14], [15], [16], [17], [18], [19] over other major semiconductor materials. Furthermore, Ge condensation [20] is an appealing technique to incorporate Ge on the Si platform because of its excellent compatibility with the incumbent Si CMOS technology [21], [22], [23], [24], [25] and the ease of controlling the thickness of GOI layers [26] over many other techniques such as Smart Cut process [27], [28], [29], direct wafer bonding (DWB) [30], [31], [32], and aspect ratio trapping (ART) [33], [34], [35]. Therefore, Ge condensation is quite effective to realize ultrathin body (UTB) architecture [36] which is indispensable in maintaining excellent electrostatic control against short channel effects (SCEs) and reducing the device performance variations with less doping, the junction leakage current, and the parasitic capacitance for 10 nm technology and beyond.

It is known, however, in Ge condensation that there is a critical issue of unpractically-large positive V_th shifts [37], [38], [39], [40] for front and back channel of SiGe/Ge-on-insulator (SGOI/GOI) pMOSFETs, and subsequently-high I_off due to parasitic conduction at the back interface [41]. Actually, there have been debates on the root cause of this issue. Here, one possible root cause can be holes arising from defect generation during the condensation process [42], [43], [44]. Accordingly, many efforts have been leveraged to passivate the crystal imperfections by N₂, H₂, D₂, Al, and Al₂O₃ [45], [46], [47], [48], [49]. On the other hand, another possible origin of this issue can be high-density interface states with the energy level locating in the Ge band gap close to the valence band edge [50], [51], [52], which has been proposed by the experimental analyses and modeling of the temperature dependence of V_th of GOI pMOSFETs with the consideration of dangling bond states at the back interface (Ge/BOX) [41]. In order to avoid this problem, counter-doping in the superficial Ge layers [38] and/or strong positive back-gate voltage [41] have been used to decouple the front and the back interfaces. The awareness of the importance of the back interface has been raised with strong interest in high quality UTB GOI layers, nevertheless no technique has been reported to engineer the quality of the back interface of GOI films for well-suited V_th and suppression of high I_off.

In this paper, we present the effects of additional oxidation after Ge condensation on electrical properties of FDGOI pMOSFETs with an emphasis on the ability to engineer the quality of the back interface by the additional oxidation. The electrical characteristics of the fabricated GOI pMOSFETs were systematically evaluated with varying the oxidation time and the resultant compressive strain values were confirmed by Raman spectroscopy. 12-nm-thick GOI pMOSFETs with 0.94 % compressive strain were realized without any additional oxidation, thanks to the initial tensile sSOI substrates used for Ge condensation, demonstrating the drive current over twice as high as that of unstrained Ge pMOSFETs. On the other hand, the devices exhibit large positive V_th shifts, degraded SS, and high I_off stemming essentially from the inferior back interface, which can be effectively improved by additional oxidation after Ge condensation without significant growth of BOX.

In order to elaborate the effects of this additional oxidation, the changes in strain and crystalline quality of GOI layers are highlighted together with electrical characterization of GOI pMOSFETs. The additional oxidation indeed leads to the restoration of the V_th shifts, improved SS, and the dramatic reduction of I_off by passivating the back interface. It is also found that the improvement of the back interface and the strain relaxation occur simultaneously by the additional oxidation, which might be due to the fact that the interstitial oxygen provided during the oxidation forms Ge–O bonds that are softer than Si–O bonds at the back interface. This could possibly facilitate the slippage of the GOI films on BOX, leading to the strain relaxation (partially, elastic relaxation via viscous flow of BOX), which is immune to dislocation generation and plastic deformation of the underlying BOX [53], [54]. Finally, a possible physical model to explain the observed phenomena was proposed.

The section organization of this paper is as follows. In Section 2, we describe the fabrication procedure of GOI layers and their structural analysis by Raman spectroscopy. In Section 3, the fabrication process flow of GOI pMOSFETs is delineated with a comprehensive study of the electrical properties of GOI pMOSFETs performed. In Section 4, conclusions are drawn.