Effects of additional oxidation after Ge condensation on electrical properties of germanium-on-insulator p-channel MOSFETs
Introduction
Large scale integrated circuits (LSIs) have been driven mainly by dimension scaling with the advent of the Moore’s law as guided in [1]. However, performance gain in sub-100 nm regime has diminished due to high external resistance and more importantly, source injection velocity of Si [2], [3], [4], [5], [6], [7], [8], presenting a plethora of challenges to continue the historic progress. To circumvent the challenges in boosting device performance, various technology knobs such as strained Si, SiGe channels, high-k/metal-gate, extremely thin silicon on insulator (ETSOI) and multi-gate structures have been implemented from the 90 nm technology node. Among a variety of the technology boosters, utilizing channel materials with high mobility and resultant high injection velocity is a very attractive option at low power supply voltage [9], [10], [11].
Germanium is one of the most promising channel materials for complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs), in particular, pMOSFETs, because of its inherently superior hole mobility and light hole effective mass [12], [13], [14], [15], [16], [17], [18], [19] over other major semiconductor materials. Furthermore, Ge condensation [20] is an appealing technique to incorporate Ge on the Si platform because of its excellent compatibility with the incumbent Si CMOS technology [21], [22], [23], [24], [25] and the ease of controlling the thickness of GOI layers [26] over many other techniques such as Smart Cut process [27], [28], [29], direct wafer bonding (DWB) [30], [31], [32], and aspect ratio trapping (ART) [33], [34], [35]. Therefore, Ge condensation is quite effective to realize ultrathin body (UTB) architecture [36] which is indispensable in maintaining excellent electrostatic control against short channel effects (SCEs) and reducing the device performance variations with less doping, the junction leakage current, and the parasitic capacitance for 10 nm technology and beyond.
It is known, however, in Ge condensation that there is a critical issue of unpractically-large positive Vth shifts [37], [38], [39], [40] for front and back channel of SiGe/Ge-on-insulator (SGOI/GOI) pMOSFETs, and subsequently-high Ioff due to parasitic conduction at the back interface [41]. Actually, there have been debates on the root cause of this issue. Here, one possible root cause can be holes arising from defect generation during the condensation process [42], [43], [44]. Accordingly, many efforts have been leveraged to passivate the crystal imperfections by N2, H2, D2, Al, and Al2O3 [45], [46], [47], [48], [49]. On the other hand, another possible origin of this issue can be high-density interface states with the energy level locating in the Ge band gap close to the valence band edge [50], [51], [52], which has been proposed by the experimental analyses and modeling of the temperature dependence of Vth of GOI pMOSFETs with the consideration of dangling bond states at the back interface (Ge/BOX) [41]. In order to avoid this problem, counter-doping in the superficial Ge layers [38] and/or strong positive back-gate voltage [41] have been used to decouple the front and the back interfaces. The awareness of the importance of the back interface has been raised with strong interest in high quality UTB GOI layers, nevertheless no technique has been reported to engineer the quality of the back interface of GOI films for well-suited Vth and suppression of high Ioff.
In this paper, we present the effects of additional oxidation after Ge condensation on electrical properties of FDGOI pMOSFETs with an emphasis on the ability to engineer the quality of the back interface by the additional oxidation. The electrical characteristics of the fabricated GOI pMOSFETs were systematically evaluated with varying the oxidation time and the resultant compressive strain values were confirmed by Raman spectroscopy. 12-nm-thick GOI pMOSFETs with 0.94 % compressive strain were realized without any additional oxidation, thanks to the initial tensile sSOI substrates used for Ge condensation, demonstrating the drive current over twice as high as that of unstrained Ge pMOSFETs. On the other hand, the devices exhibit large positive Vth shifts, degraded SS, and high Ioff stemming essentially from the inferior back interface, which can be effectively improved by additional oxidation after Ge condensation without significant growth of BOX.
In order to elaborate the effects of this additional oxidation, the changes in strain and crystalline quality of GOI layers are highlighted together with electrical characterization of GOI pMOSFETs. The additional oxidation indeed leads to the restoration of the Vth shifts, improved SS, and the dramatic reduction of Ioff by passivating the back interface. It is also found that the improvement of the back interface and the strain relaxation occur simultaneously by the additional oxidation, which might be due to the fact that the interstitial oxygen provided during the oxidation forms Ge–O bonds that are softer than Si–O bonds at the back interface. This could possibly facilitate the slippage of the GOI films on BOX, leading to the strain relaxation (partially, elastic relaxation via viscous flow of BOX), which is immune to dislocation generation and plastic deformation of the underlying BOX [53], [54]. Finally, a possible physical model to explain the observed phenomena was proposed.
The section organization of this paper is as follows. In Section 2, we describe the fabrication procedure of GOI layers and their structural analysis by Raman spectroscopy. In Section 3, the fabrication process flow of GOI pMOSFETs is delineated with a comprehensive study of the electrical properties of GOI pMOSFETs performed. In Section 4, conclusions are drawn.
Section snippets
Fabrication procedure and structural analysis of GOI by Ge condensation
Utilizing tensile sSOI as an initial platform of choice for Ge condensation to mitigate lattice mismatch to Ge and the performance of devices realized on the platform were first demonstrated in [55]. The initial tensile strain in the substrates alleviates strain relaxation during condensation process, because of smaller lattice mismatch to Ge than conventional unstrained SOI substrates, resulting in improved crystallinity of condensed SiGe/Ge films and suppression of the degradation of back
Electrical characterization
In order to investigate the electrical properties of GOI layers with different back interface structures after the additional oxidation, top gated GOI pMOSFETs were fabricated. The changes in Vth, SS, Ioff, and hole mobility were characterized through I–V and C–V measurements.
Conclusions
We systematically studied the impacts of additional oxidation after Ge condensation on GOI structures and electrical properties of GOI pMOSFETs. 12-nm-thick GOI pMOSFETs without additional oxidation show the drive current over twice as high as that of unstrained Ge pMOSFETs owing to compressive strain, thanks to the initial sSOI substrates. However, the devices present large positive Vth shifts and high Ioff due to parasitic conduction ascribed to the inferior back interface, which can be
Acknowledgements
This work was partly supported by a Grant-in-Aid for Scientific Research (Nos. 18063005 and 23246058) from the Ministry of Education, Culture, Sports Science, and Technology in Japan.
References (72)
- et al.
Device structures and carrier transport properties of advanced CMOS using high mobility channels
Solid State Electron
(2007) - et al.
Germanium-on-insulator (GeOI) substrates-A novel engineered substrate for future high performance devices
Mater Sci Semicond Process
(2006) - et al.
Defect delineation and characterization in SiGe, Ge and other semiconductor-on-insulator structures
Solid State Electron
(2009) - et al.
Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques
Solid State Electron
(2004) - et al.
Ultrathin layer transfer technology for post-Si semiconductors
Microelectron Eng
(2013) - et al.
High performance 70 nm gate length germanium on insulator pMOSEFTs with high-k/metal gate
Solid State Electron
(2009) - et al.
Impact of strain on the passivation efficiency of Ge dangling bond interface defects in condensation growth SiO2/GexSi1−x/SiO2(1 0 0)Si structures with nm-thin GexSi1−x layers
Appl Surf Sci
(2014) - et al.
A thermodynamic model for the growth of buried oxide layers by thermal oxidation
Mater Sci Eng B
(1996) - et al.
Raman spectroscopy determination of composition and strain in Si1−xGex/Si heterostructures
Mater Sci Semicond Process
(2008) - Dennard RH, Gaensslen FH, Kuhn L, Yu HN. Design of micron MOS switching devices. In: IEDM tech dig; 1972. p....
Technology for advanced high-performance microprocessors
IEEE Trans Electron Dev
On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?
IEEE Electron Dev Lett
Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress
IEEE Electron Dev Lett
On the mobility versus drain current relation for a nanoscale MOSFET
IEEE Electron Dev Lett
Essential physics of carrier transport in nanoscale MOSFETs
IEEE Trans Electron Dev
Carrier-transport-enhanced channel CMOS for improved power consumption and performance
IEEE Trans Electron Dev
Considerations for ultimate CMOS scaling
IEEE Trans Electron Dev
High electron mobility Ge/GeO2 n-MOSFETs with two-step oxidation
IEEE Trans Electron Dev
High mobility Ge p-and n-MOSFETs with 0.7-nm EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation
IEEE Trans Electron Dev
A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs
Jpn J Appl Phys
High mobility strained SiGe on insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique
IEEE Electron Dev Lett
GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current
IEEE Trans Electron Dev
Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique
Appl Phys Lett
Characteristics of germanium-on-insulators fabricated by wafer bonding and hydrogen-induced layer splitting
Jpn J Appl Phys
Ultrathin-body Ge on insulator wafers fabricated with strongly bonded thin Al2O3/SiO2 hybrid buried oxide layers
Appl Phys Express
Cited by (7)
Strain evolution in SiGe-on-insulator fabricated by a modified germanium condensation technique with gradually reduced condensation temperature
2019, Materials Science in Semiconductor ProcessingEffect of post annealing on hole mobility of pseudo-single-crystalline germanium films on glass substrates
2017, Materials Science in Semiconductor ProcessingCitation Excerpt :Thus, we emphasize that, to achieve high-performance p-TFTs with PSC-Ge layers, the crystal quality of the PSC-Ge films should be improved. As described in Introduction section, some post annealing processes are effective to improve electrical properties of Ge layers formed on glass substrates (SiO2) [13–16]. Thus, we performed PA in N2 atmosphere (400 °C, 30 min).
Introduction of high tensile strain into Ge-on-Insulator structures by oxidation and annealing at high temperature
2022, Japanese Journal of Applied PhysicsNew Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET
2021, ACS Applied Materials and Interfaces