A graph based approach for reliability analysis of nano-scale VLSI logic circuits
Introduction
New advances in the fabrication of logic circuits and scaling down to a few nanometers have resulted in logic circuits that are more susceptible to failure. Process variability, soft errors due to cosmic rays and neutron particles are potential causes of the circuit failure [1], [2]. Transistor reliability issues such as negative and positive bias temperature instability (NBTI, PBTI), threshold voltage shift and mobility degradation in new VLSI manufacturing technologies have resulted in reduced reliability of logic circuits [3], [4]. Furthermore, the circuits in newer VLSI manufacturing technologies are more prone to dynamic errors caused by reduced noise margin, lower supply voltage and low stored charge in circuit nodes [5].
Reliability analysis of logic circuits is defined as the process of evaluating the effect of errors on a circuit’s output nodes [6]. Accuracy, runtime, scalability, computational complexity, memory requirements and single or multiple error occurrences are the main issues considered in reliability analysis.
When an error occurs at a node it propagates through the circuit and it can incorrectly change the state of the circuit, or undesirably affects the primary outputs of the circuit, both resulting in a failure. The rate of exposure of each circuit’s node to errors depends on the circuit and environmental conditions. Particles hit rate, supply voltage, node capacitance, NMOS or PMOS transistors, transistor size, temperature, circuit type (static or dynamic), number of gate inputs and even the order of placement of gate inputs are some of the important issues that affect the error rate at each node [5].
Single-pass [6], analytical approaches [7], Markov random fields [8], Probabilistic transfer matrices (PTM) [9], [10], [11], [12], probabilistic model checking (PMC) [13], symbolic techniques [14], [15], Bayesian networks (BN) [16], [17], [18], error propagation probability (EPP) [19], [20], [21], [22], probabilistic decision diagrams (PDD) [23], probabilistic gate model (PGM) [24], [25], signal probability reliability analysis (SPRA) [26], [27], [28], improved form of single-pass [29], signature based (AnSER) [30], stochastic computational model (SCM) [31], [32], trigonometry based methods [33], cross-talk PTM [34] and correlated error propagation (CEP) [35] are some approaches reported in the literature for reliability evaluation of logic circuits.
In general, there is a compromise between accuracy and computational complexity in all of these approaches. For example, while PTM and PDD are accurate, they are limited to small circuits. However, other approaches that are capable of analyzing larger circuits with lower accuracy are limited in terms of circuit size due to high computational complexity. Thus, the growth in size of new advanced VLSI circuits demands new approaches to analyze their reliability with low computational complexity and sufficient accuracy.
In this paper, a new method based on a modified form of Mason’s rule is proposed to analyze the reliability of VLSI logic circuits at the presence of multiple independent errors. The closed matrix formulation and employing matrix sparsity [36] make it capable of analyzing large circuits. Employing the fixed-point theorem makes this algorithm very fast. Finally, using a Monte-Carlo framework with few number of iterations, the effects of reconvergent paths is also considered. The proposed approach is scalable, and a considerable improvement in computational time has been achieved compared with the best existing approaches.
The rest of the paper is organized as follows. Error propagation modeling in logic circuits is presented in Section 2. The probabilistic model for logic gates is introduced in Section 3. Reliability evaluation algorithm is described in Section 4. Simulation results are presented in Section 5. Finally the paper is concluded in Section 6.
Section snippets
Error propagation modeling
Errors are mainly modeled based on the Von Neumann model [37], which implies that each error changes the output of a gate to an incorrect value (as opposed to stuck-at faults). If each error appears at a gate with a constant rate, the error probability (EP) in next gates is computed based on the interaction of gate’s error and gate inputs error. Thus a gate generates an erroneous output while its inputs are correct, or it operates properly but because of incorrect inputs, it generates erroneous
Logic domain and probabilistic domain
In general, the output of a gate is related to its inputs using a Boolean equation. Using min-term abstract, the general form of a Boolean equation of a gate is equal to [7]:where yj is the gate input or its inverted version () and mi is the ith min-term. Since, summation and product terms used in (4) are Boolean operations, the output is also Boolean. The probabilistic domain is the probabilistic equivalents for (4) as follows [7]:
Reliability evaluation algorithm
Based on the probabilistic model introduced in Section 3, the reliability of the circuit is computed in two phases. In first phase, the circuit is assumed to be error-free and the transmittance matrices for its PSFG are constructed using Table 3. Then SP values are found. In second phase, using SP values in first phase, for the error-prone circuit, transmittance matrices are constructed and EP values are computed. Finally, EP values at the primary outputs are used to find the overall circuit
Simulation results
Several benchmark circuits are used to compare the effectiveness and speed of the proposed approach with the existing methods. All simulations were performed on a Latitude D630 system with 2 GHz Core 2 Duo processor and 2 GB of RAM memory. The required framework for the proposed approach runs under MATLAB environment. All gates are assumed to have the same error rate.
Table 7 shows the evaluation results for some ISCAS’85 combinational logic benchmarks with the gate error rate (ε) set to 0.05. The
Conclusion
This work proposes a new and fast method to analyze the reliability of logic circuits based on a modified form of Mason’s rule. The reliability of the circuit is computed using its equivalent probabilistic SFG (PSFG) and the problem of finding circuit probabilities is converted to the problem of finding the solution of a system of nonlinear equations obtained using Mason’s rule. Fixed-point iterations are utilized to obtain the solution of this system of equations.
All computations are handled
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2015, Microelectronics ReliabilityCitation Excerpt :However, applying all possible combinations of ‘0’ or ‘1’ to the proposed approach leads to an exponential computational complexity. To resolve both the aforementioned problems due to reconvergent paths effects, while the scalability of the approach is preserved, a low-iteration Monte-Carlo (MC) simulation with 256 iterations is utilized [7,31]. As another source of inaccuracy at reconvergent fanouts, when both inputs of a node satisfy the case (2) introduced in section II, MGF yields incorrect results.
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