Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric
Introduction
3D integration based on Through Silicon Via (TSV) is becoming an attractive alternative to overcome obstacles of CMOS scaling. The vertical stack of dice, using chip-to-chip interconnects and TSV, enables higher bandwidths and smaller footprints.
TSV technologies for mainstream integration schemes, such as Wide IO memory stacking [1], [2], [3] or TSV based passive interposers, appear today to crystallize around 5–10 μm diameter Cu TSV in 50–100 μm thick silicon. Whatever the presence of active devices in the Si strata having TSVs, first reliability concerns are located at interfaces of TSV and at adjacent metallization levels. And since TSV processes reach today maturity, reliability investigations become critical.
Early reliability studies of TSV based integrations started during the last decades with thermo-mechanical simulations, since the thermal expansion mismatch between Cu TSV and Si die is very large: Si and Cu Coefficient of Thermal Expansion (CTE) are respectively of about 3 × 10−6 °C−1 and 17 × 10−6 °C−1. Several studies evaluated, through simulations, fatigue of Cu TSV, delamination at TSV interfaces, and Si cracking due to thermo-mechanical stress. These studies point out that the existence of the copper through-vias affects the stress distributions and the interconnection reliability [4], [5], [6], [7], [8], [9]. Maximum computed stresses, and related expected failures in the TSV, are localized at interfaces to adjacent metal levels [4], [6]. Consequently, early experimental reliability studies of TSV, focused on Thermal Cycling (TC) assessments [10], [11], [12]. However, authors underlined the overall robustness of TSV interconnects.
Besides TC, mainly three other failure mechanisms have been recently started to be studied for TSV based integrations: Electromigration (EM) induced voiding due to matter flux divergence at TSV interfaces [13], [14], [15], [16], [17]; impact of TSV on adjacent Back End of Line (BEoL) dielectrics reliability [18], [19]; and Cu diffusion from TSV into active silicon [20], [21]. Regarding EM, most studies focus on matter flux diffusion modeling at TSV interfaces [13], [14], [15]. However, these models lack of metallization barrier (like TaN or TiN) between the TSV and the adjacent metal levels. These barriers, today integrated in all the main-stream TSV interconnects, are a key item regarding the matter flux divergence due to electromigration.
In this paper, concerns of TC, EM, and impact of TSV on adjacent BEoL dielectric reliability, are addressed following two parts. First part presents an exhaustive experimental analysis of a high density Cu TSV-last technology of 2–4 μm diameters, and 15 μm of depth: TC and EM stresses are performed on dedicated devices focusing at TSV interfaces. Second part covers experimental reliability of Cu TSV-middle technology of 10 μm diameter and 80 μm thickness. TC, impact of TSV on BEoL dielectric breakdown, and EM degradation are addressed.
Note that the key difference between the concepts of TSV-last and TSV-middle, is related to the process sequences: TSV-last, stands for integrations for which TSV is processed after the BEoL interconnects. For TSV-middle, the TSV is processed after Front End of Line (FEoL) and before BEoL. Although this difference is critical regarding thermal budgets of processes, the reliability issues are comparable, since related TSV interfaces are similar for both TSV-last and TSV-middle approaches.
Section snippets
Process description
A test vehicle has been designed and fabricated to analyze process, electrical performances and reliability of a high density Cu TSV-last technology, with diameters in the range of 2–5 μm, processed in a 15 μm thick Si strata. First process and electrical performances have been addressed in previous papers [22], [23]. Concerning reliability, the test vehicle contains structures dedicated to address mainly TC and EM stresses. Since no chip-to-chip interconnects, i.e. solder bumps, are required to
Process description
Similarly to above TSV-last test vehicles, a test vehicle based on TSV-middle approach has been designed and fabricated in a 65 nm CMOS node with six metal layers of BEoL. Cu TSV has a diameter of 10 μm and depth of 80 μm.
The main steps of the Cu TSV middle process are (Fig. 16): (1) TSV etching achieved with a Bosch Deep Reactive Ion Etching (DRIE); (2) deposition of a SiO2 isolation layer, a Ta barrier deposition, Cu seed and electrolytic filling; (3) usual Cu damascene 65 nm node metal layers
Conclusion
In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two technologies: high density Cu TSV-last and Cu TSV-middle. For both technologies, mature processes ensure to pass Thermal Cycling assessments for Kelvin TSV devices. Studies of electromigration behavior reveal that for both technologies, voiding is located above the TSV, in the adjacent metal level. In case of usual thin metallization level, void nucleation and Cu diffusion under electromigration occur at
Acknowledgments
The authors would like to thank Process Integration, Physical Characterization, Design, Reliability and Assembling teams in STMicroelectronics and CEA-LETI that have been involved in the realization of this study.
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