Elsevier

Microelectronics Reliability

Volume 50, Issues 9–11, September–November 2010, Pages 1789-1795
Microelectronics Reliability

Reliability of planar, Super-Junction and trench low voltage power MOSFETs

https://doi.org/10.1016/j.microrel.2010.07.042Get rights and content

Abstract

A strong demand of even more compact and reliable devices has powered in the last years the development of advanced power MOSFET structures. Among them, the planar STripFET™ has been introduced as an alternative to conventional trench gate MOSFET in low voltage (<60 V) applications. Moreover low voltage Super-Junction devices are also under development. In this paper a conventional trench gate MOSFET is compared in terms of reliability with a STripFET™ and a Super-Junction device. The comparison is accomplished through a reliability model taking advantage from a dynamic analysis of the temperature distribution over the metal source surface in an effort to correlate electric working conditions to thermo-mechanical stresses.

Introduction

Modern low voltage (VDSBR < 60 V) power MOSFETs feature a quite low on state resistance (RDSON), a high switching speed and a very low drive power, closely resembling the characteristics of ideal switches. This is the result of an evolution started more than 30 years ago, when the first planar power MOSFET structure was developed, featuring a channel built on the silicon surface by mean of a double-diffusion process. On early planar devices the on state resistance RDSON was dominated by the channel region resistance, although noticeable contributions were also given by: JFET and accumulation layer, drift region, and parasitics (metallization, bond wires, and package) resistance. From their introduction planar power MOSFETs were gradually improved by progressively increasing the cell density to reduce the channel resistance. However, some technological limitations were impacted as cell density enhancements affect the gate capacitance, increasing the switching power losses. An alternative structure was developed 20 years ago setting a new standard for low voltage power MOSFET devices. As shown in Fig. 1, such a structure features a MOS channel vertically deployed along the sidewalls of a trench etched into the silicon surface, greatly enhancing the channel density and eliminating the JFET and accumulation layer resistance component. This enabled the realization of cost competitive trench gate devices featuring a remarkably smaller die size than their planar counterparts. However, such a smaller and less expensive structure often gives also a reduced avalanche capability. Some advanced structures have been also recently introduced in an attempt to improve the performances [1], [2]. Among them, Super-Junction (S-J) devices are well suited for power integrated circuit applications. On this kind of devices the drift region resistance is dramatically reduced by increasing of one order of magnitude the doping of the drift region and inserting additional vertical p-stripes, or pillars, to compensate the surplus current conducting n-charges, as shown in Fig. 1. Low voltage S-J MOSFETs have been recently developed featuring a RDSON better to that planar and close to gate trench devices by optimization of the geometry of pillars and the doping levels.

On the discrete devices side, revised planar structures, such as the STripFET shown in Fig. 1, have been recently introduced, where the RDSON is noticeably lowered if compared with the early planar structures. This makes new planar devices competitive with discrete trench MOSFETs. In fact, while featuring on resistances approaching those of trench devices, they show a lower Miller capacitance and shorter rise and fall times, enabling switching operations up to 1 MHz. Moreover, thanks to the introduction of a vertical micro trench contact in last generation STripFETs, the silicon area dedicated to the short-circuit between the Body and the Source is noticeably reduced, so increasing the density of elementary cells and further lowering the RDSON.

Planar, S-J and trench MOSFETS are today competing on low voltage (<60 V) applications in SMPS, automotive and lighting fields, having a target market of several billions of devices per year. The competition is played in terms of rated current, cost and reliability. However, while several papers have been published in the past, where planar, S-J and trench MOSFETS are compared in terms of rated current and cost, little was done about reliability comparison.

In low voltage applications the effects of repeated avalanche operations are crucial for the lifetime of MOSFETs. Therefore, it is important to estimate how many avalanche operations a device can withstand before failure. This can be experimentally accomplished through endurance tests. Alternatively, the ability of power devices to support repetitive avalanche operations can be estimated by reliability models. In this paper the last approach is adopted. The specific reliability model exploited in this paper takes advantage from an experimental thermodynamic analysis of the source metallization of the devices. Through such an analysis it is possible to correlate the characteristics of avalanche operations with the amplitude and the distribution of thermo-mechanical stresses.

Section snippets

Reliability issues due to repetitive avalanche cycles

Avalanche is a quite critical working condition for any power MOSFET. In low voltage applications, avalanche operations may be the unforeseen result of the energy trapped in leakage and stray inductances, or an expected repetitive working condition.

The robustness of low power MOSFETs against avalanche operations generated by inductive over voltages is generally given in terms of rated single pulse avalanche energy, appraising how much reverse avalanche energy the device can safely withstand.

Reliability model

Main parameters determining the degradation of the metal source and the increment of the on state resistance in repetitive avalanche operations are junction temperature rise during the thermal cycle ΔTj, and the number of avalanche cycles Ni. Therefore, a reliability model structure has been selected, based on the Coffin–Manson law. Such a law is typically used to deal with solder cracking caused by temperature cycling in electronic components [6], [7]. The selected reliability model is based

Experimental temperature measurement

The Coffin–Manson law gives the number of cycles to failure as function of the maximum temperature variation, while a device mission profile is normally specified in terms of load current and ambient temperature. Therefore, the load current must be correlated to the maximum temperature rise in the junction. However, it is not sufficient to consider the average temperature of the metal surface, as the spatial distribution of the temperature may result strongly uneven.

A possible way to relate the

Life time estimation

In order to properly compare the reliability performances of the three considered kinds of MOSFET, obtained results must be suitably managed to account for the different characteristics of the tested devices.

According to Table 1, two of the three tested devices feature a 29 mm2 die size, while the die size of the S-J MOSFET is only 6 mm2, although the current density is similar. Assuming approximately uniform the power dissipation over the metal, the drain current of the S-J device has been

Conclusion

A conventional trench gate MOSFET has been compared in terms of reliability with a STripFET and a low voltage Super-Junction device exploiting suitable reliability models developed from the Coffin–Manson curve. Identification of model parameters has been accomplished by accelerated stress test. Peak drain current has been correlated to the maximum temperature raise in the junction during an operative cycle exploiting a dynamical thermal mapping approach. Suitable compensation factor have been

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