A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s

doi:10.1016/j.microrel.2008.11.005

Microelectronics Reliability

Volume 49, Issue 2, February 2009, Pages 113-119

https://doi.org/10.1016/j.microrel.2008.11.005 Get rights and content

Abstract

On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the short-channel tri-material gate-stack SOI MOSFET’s is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.

Introduction

Due to the advancement of the gate material engineering, dual-material gate (DMG) MOSFET’s has been investigated and expected to suppress the short-channel effects (SCEs) and enhance the carrier transport efficiency [1], [2]. The DMG MOSFET will induce the step potential at the interface between the different gate materials and make a peak electric field in the channel region that improves the carrier transit speed and increases the device driving capability. Owing to the screen effects from the device having gate material with low work function, the high electric field near the drain side can be effectively reduced, which suppresses the hot carrier effects (HCEs) and reduces the substrate current leakage. During the last decade, high-k dielectrics have been studied as an alternative to SiO₂ based gate dielectric to reduce the gate leakage current and the use of high-k materials in the oxide region can effectively reduce gate leakage current with continuous thinning of gate oxide layer [3]. The gate-stack structure with a gate oxide of SiO₂ as a interfacial buffer between bulk silicon and high-k dielectrics can screen the effect of phonon scattering and improve the carrier mobility [4]. The straddle-gate structure with three materials as gate electrode was proposed by Tiwari et al. [5] to reduce source-to-drain leakage current due to the threshold voltage of the side gates that is smaller than that of the main gate. Cooperating the advantage of gate-stack with straddle-gate structure, Gupta et al. [6] suggested a new device structure that is so-called the tri-material gate-stack (TRIMGAS) MOSFET as shown in Fig. 1. They also developed the analytical model of the short-channel TRIMGAS MOSFET on the basis of the quasi-two-dimensional (quasi-2D) potential approach. However, the inherent drawback of the large errors in predicting the potential profile near the source/drain [7] makes quasi-2D potential approach inaccurate to portray the two-dimensional (2D) potential contours which are essential for demonstrating the electric characteristics of the devices. Moreover, one of the key performance parameters that plays a very important role in digital circuit evaluation such as subthreshold current is not accounted for in their work. To precisely analyze the short-channel TRIMGAS SOI MOSFETs when it is applied for the digital circuits, it is mandatory to develop the exactly 2D subthreshold behavior model. In this work, on the basis of the exact solution of 2D Poisson equation, we successfully developed a new compact subthreshold behavior model comprising 2D potential, threshold voltage, and sunthreshold current. The calculated results of the model match well with those simulated of the device simulator MEDICI [8]. Beside giving a physical insight into the device physics, the model provides guidance for the basic design for the short-channel TRIMGAS SOI MOSFETs.

Section snippets

Two-dimensional potential model

Since the free carrier concentration is much less than the impurity density for MOSFETs operating in subthreshold regime, the Poisson equation in the short-channel TRIMGAS SOI MOSFETs can be divided into three regions and expressed as $\frac{\partial^{2} Φ_{1} (x, y)}{\partial x^{2}} + \frac{\partial^{2} Φ_{1} (x, y)}{\partial y^{2}} = \frac{{qN}_{a}}{ϵ_{si}} 0 ⩽ x ⩽ L_{1}, 0 ⩽ y ⩽ t_{si}$ $\frac{\partial^{2} Φ_{2} (x, y)}{\partial x^{2}} + \frac{\partial^{2} Φ_{2} (x, y)}{\partial y^{2}} = \frac{{qN}_{a}}{ϵ_{si}} L_{1} ⩽ x ⩽ L_{2}, 0 ⩽ y ⩽ t_{si}$ $\frac{\partial^{2} Φ_{3} (x, y)}{\partial x^{2}} + \frac{\partial^{2} Φ_{3} (x, y)}{\partial y^{2}} = \frac{{qN}_{a}}{ϵ_{si}} L_{2} ⩽ x ⩽ L_{3}, 0 ⩽ y ⩽ t_{si}$ where the channel doping of N_a is assumed to be uniform and the x-axis is perpendicular and the y-axis is parallel to the

Results and discussion

To verify the 2D model of the short-channel devices, Fig. 2 shows the variation of the surface potential Φ(x, 0) with the normalized channel position for different gate materials with the ratios of $L_{M_{1}}$ , $L_{M_{2}}$ , and $L_{M_{3}}$ . Good agreement between the results of our model and those of device simulator is obtained. The plot indicates that the minimum surface potential barrier between the source side and the minimum channel position of x_min can be increased for the high ratio of $L_{M_{1}}$ , $L_{M_{2}}$ , and $L_{M_{3}}$ such as

Conclusions

Based on the exact 2D solution of Poissons equation, a new analytical compact subthreshold behavior model comprising 2D channel potential, threshold voltage, and subthreshold current for a short-channel TRIMGAS MOSFET SOI MOSFET has been successfully developed. It is found that a thin effective stack-gate oxide thickness, a thin silicon body and a large ratio of $L_{M_{1}}$ to $L_{M_{2}}$ are required to provide the device with good subthreshold behavior. The accurate model results make it useful to predict

References (14)

G.V. Reddy et al.
A new dual-material double-gate (DMDG) nanoscale SOI MOSFET – two-dimensional analytical modeling and simulation
IEEE Trans Electron Dev
(2005)
M. Saxena et al.
Physics-based modeling and simulation of dual-material gate stack (DUMGAS)MOSFET
Electron Lett
(2003)
Q. Lu et al.
Leakage current comparison between ultra-thin Ta₂O₅ films and conventional gate dielectrics
IEEE Trans Electron Dev Lett
(1998)
B.H. Lee et al.
Metal electrode/high-k dielectric gate-stack technology for power management
IEEE Trans Electron Dev
(2008)
Tiwari S, Welser JJ, Kumar A, Cohen S. Straddle gate transistors: high Ion/Ioff transistors at short gate lengths. In:...
K. Goel et al.
Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects
IEEE Trans Electron Dev
(2006)
K.K. Young
Short-channel effect in fully depleted SO1 MOSFET’s
IEEE Trans Electron Dev
(1989)

There are more references available in the full text version of this article.

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View full text

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s

Abstract

Introduction

Section snippets

Two-dimensional potential model

Results and discussion

Conclusions

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET – two-dimensional analytical modeling and simulation

IEEE Trans Electron Dev

Physics-based modeling and simulation of dual-material gate stack (DUMGAS)MOSFET

Electron Lett

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

IEEE Trans Electron Dev Lett

Metal electrode/high-k dielectric gate-stack technology for power management

IEEE Trans Electron Dev

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

IEEE Trans Electron Dev

Short-channel effect in fully depleted SO1 MOSFET’s

IEEE Trans Electron Dev

Leakage current comparison between ultra-thin Ta₂O₅ films and conventional gate dielectrics