Elsevier

Microelectronics Reliability

Volume 48, Issues 8–9, August–September 2008, Pages 1586-1591
Microelectronics Reliability

Signal probability for reliability evaluation of logic circuits

https://doi.org/10.1016/j.microrel.2008.07.002Get rights and content

Abstract

As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence.

Introduction

The continuous reduction in the dimensions of integrated circuits has raised some serious problems to the implementation of nanometric circuits, like power consumption and dissipation, current leakage and parametric variations. Many of these problems lead to a reduction in the reliability of CMOS devices [1], [2], [3], what can seriously compromise the gains attained with technology scaling.

The reliability of a logic circuit is a measure of its susceptibility to permanent, intermittent and transient faults. In the current work, the focus is on evaluating the reliability of combinational logic circuits concerning intermittent and transient faults, i.e., faults originated from soft errors, thermal bit-flips, parametric variations, among others. Historically, transient errors were a concern in the design of memory elements, but the susceptibility of the combinational blocks to transient faults increases as a side effect of technological scaling.

The protection of memory elements is fairly simple and do not impose critical overheads, due to the fact that memories deal with static data. On the other way, the protection of the logic blocks in a circuit is a much more complicated task and is associated with important overheads in terms of area, time and power. Fault-tolerant architectures, like the ones discussed in [4], [5], [6], have been historically targeted to mission critical applications, where reliability improvement and fault secureness are the main design objectives and the resulting overheads can be accepted.

With the expected reduction in the reliability of nanoscale CMOS, logic blocks will become the focus of hardening techniques, but in these cases, the associated overheads must be minimized to guarantee some gain in the scaling process. To cope with these tighter design constraints, partial fault tolerance [7], [8] and fault avoidance techniques [9], [10], [11] can be considered. In the referred techniques, fine-grain improvements in the reliability of gates/cells are possible, minimizing the overheads in area, delay and power of the overall circuit.

In this context, a fast and accurate evaluation of circuit’s reliability is fundamental, to allow an automated reliability-aware design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. Unfortunately, reliability analysis is a complex task, and computing its exact value is intractable for practical circuits.

Different methodologies have been proposed to evaluate the reliability of combinational circuits, like in [12], [13], [14], [15], where the computation of the exact reliability value limits the size of the target circuits, or in [16], [17], [18], where simplified assumptions, like single-output, single-fault or single-path limit the results of the analysis. Furthermore, most of these methodologies are based on external software packages or simulation, difficulting its integration to an automated design flow.

The current work proposes the use of signal probability as an indication of the signal reliability [12] of logic circuits, taking into account the occurrence of multiple simultaneous faults. Based on a straightforward signal probability computation algorithm, the methodology allows the evaluation of the logical masking capability of combinational circuits and can be used to analyze the effectiveness of fault tolerance and fault avoidance techniques. As expected for signal probabilities computation, the main problem is the effect of signal correlations, and two heuristics are compared in the present work.

This paper is organized as follows. Section 2 reviews some concepts on signal reliability. Section 3 presents the signal probability algorithm for reliability analysis and Section 4 shows the dynamic weighted averaging and the multi-pass algorithms to reduce the effects of reconvergent fanouts in signal probabilities. Some results of the application of the method to several combinational circuits are discussed in Section 5. Section 6 presents the concluding remarks.

Section snippets

Signal reliability

Reliability (R) is an attribute with many faces, depending on the type of faults that are considered, i.e., permanent, intermittent or transient ones. In the current work, the objective is to evaluate the signal reliability of combinational logic circuits concerning transient faults. These faults can be originated from many sources, e.g., high-energy neutrons, alpha particles, thermal noise, crosstalk and voltage fluctuations.

Signal reliability concerns the failure rate of a circuit, in

Signal reliability based on signal probabilities

In the present work, we propose an algorithm to compute the cumulative effect of faults in the gates of a circuit, where a fault (transient) is modeled as a bit-flip error at the output of the faulty gate. The algorithm takes into account the reliability of circuit gates and the topological structure of the circuit to determine the probability of correctness of the signals. The computation of the cumulative effect of errors embeds the probability of occurrence of multiple simultaneous faults in

Reducing the effect of signal correlations

Given the complexity of signal probability computation, some heuristics have been proposed to reduce the effects of reconvergent fanouts, as the weighted averaging algorithm, the cutting algorithm, Stafan, Predict and the dynamic weighted averaging algorithm (DWAA) [20], [19]. Among these heuristics there are distinct tradeoffs between accuracy and processing time. In the current work the DWAA has been implemented considering that it is possibly the best option among the linear time algorithms.

Results

The algorithms presented so far were implemented in the C language, and they were developed to analyze post-synthesis circuits. A topological extraction tool has also been developed to determine circuit structure from the gate-level description (VHDL and Verilog) generated by the synthesis tool. The signal reliability is computed by specifying the reliability of the individual cells, or a range for this reliabilities, and in the case of the multi-pass algorithm, the number of fanout signals to

Conclusion

The present work has shown the use of signal probability as a valid indication of the reliability of combinational circuits. Three algorithms have been discussed and clear tradeoffs between accuracy and execution time are available. As referred before, exact results for the signal reliability characteristic of practical circuits are intractable and the use of pseudo-random simulations remains the more accurate method available for this type of analysis. Nevertheless, the proposed approaches are

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