Total ionizing dose effects in shallow trench isolation oxides
Introduction
Radiation tests of CMOS transistors in the 130 nm node from several sources show that 2.2 nm thick gate oxides are virtually unaffected by total ionizing dose (TID) irradiation up to multi-Mrd(SiO2) levels [1], [2]. This property has been confirmed by noise measurements, which have not evidenced any significant buildup of defects close to the oxide–channel interface (1/f noise is particularly sensitive to the presence of such defects) [3].
The shallow trench isolation (STI) oxide that is used to isolate transistors in this technology node still has a thickness of several 100 nm. Therefore, this oxide is expected to be very sensitive to radiation. Documented consequences of radiation-induced charge trapping in the STI seriously affecting the functionality of transistors are source–drain leakage currents in NMOS transistors and width-dependent threshold voltage shifts of both NMOS and PMOS transistors (an effect that has been called radiation-induced narrow channel effect, RINCE) [1].
All these effects have been shown to increase with TID during a continuous irradiation at laboratory dose rates (about 25 krd(SiO2)/min) and room temperature up to about 3–6 Mrd(SiO2). When irradiation is continued beyond that point under the same conditions, leakage currents and threshold voltage shifts of NMOS transistors decrease towards pre-irradiation values, while threshold voltage shifts of PMOS transistors continue to increase [1]. This is shown in Fig. 1.
To understand the radiation effects on the survival or failure of integrated circuits (ICs) in a radiation environment, it is important to consider that significant threshold voltage shifts (of magnitude ∼50–80 mV) in PMOS FETs have been observed exclusively on transistors with the smallest gate width, ΔVth becoming quickly negligible with increased W (RINCE). Therefore, the main parameters that influence the survival of the IC – the most relevant being the leakage current – are those affecting NMOS transistors and exhibiting an evolution “peaking” at a given TID level.
It has been demonstrated for MOS technologies that the value of the peak degradation typically depends on the dose rate, temperature, and applied bias voltage [4]. Therefore the radiation response of ICs in the real application can only be predicted once the main properties of the trapping centers in the STI oxide are known.
Section snippets
Test structures
The study was carried out on custom-designed samples from a commercial 130 nm CMOS technology available via a multi-project-wafer service. It concentrated on field oxide field effect transistors (FOXFETs), devices using the STI oxide as the gate dielectric, as shown in Fig. 2. The standard measurement techniques used to study radiation effects on gate oxides of MOS transistors in this case allow the study of defect buildup in the STI oxide and at its bottom interface with the silicon substrate.
Radiation-induced defects in the STI oxide
Measurements aimed at studying the characteristics of the defects induced by radiation in the STI have been performed on the FOXFETs with polysilicon gate and n-well source and drain with different techniques.
Subthreshold swing technique
The evolution of the drain current vs. gate voltage of FOXFETs irradiated with X-rays is shown in Fig. 5.
The threshold voltage Vth, extracted with a linear fit on the square root of the Id(Vgs) curve in saturation, shifts to smaller values at the beginning of the irradiation, and it later
Discussion
Our results indicate that the peaked evolution of both ΔVth and leakage current in NMOS transistors shown in Fig. 1 is determined by the balance between positive charge trapped in the bulk of the STI oxide and negative charge trapped at its interface with the silicon substrate. In the case of PMOS FETs, positive charge is trapped in both types of defects and contributes to the steady increase of the Vth in Fig. 1.
From dynamic transconductance and charge-pumping measurements, it appears that the
Summary and conclusion
A comparison of the evolution of NMOS transistor leakage and threshold voltage of FOXFETs provides a good correlation between the TID response of sidewall and bottom of the STI in a 130 nm generation technology. This suggests uniform trends in defect buildup near all STI interfaces, and indicates that FOXFETs can be effectively used to study the properties of the trapping centers responsible for NMOS source–drain leakage.
The peaked evolution of leakage current observed in NMOS transistors at
Acknowledgements
The authors are grateful to Ali Mohammadzadeh and Bob Nickson at EAS-ESTEC for their help in accessing the 60Co irradiation source for the low dose rate experiments, and for their assistance in setting up and running the irradiation test.
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