Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

Abstract

As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100 mm² without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter.

Introduction

The WLCSP technologies currently in use are attractive to the electronic packaging industry because of their excellent thermal performance, smaller size, lighter weight, etc. Similar to other electronic packages such as the flip chip package, and the ball grid array package; the reliability of the solder joints of the WLCSP without underfill remains a critical issue that needs to be resolved. A major failure mode for these above-mentioned packages is thermo-mechanical fatigue of the solder joints due to the thermal stress induced by the CTE mismatch between the silicon die and the substrate.

The solder joints reliability of the WLCSP has been a long-standing issue of interest to researchers in the advanced packaging field [1], [2], [3], [4], [5], [6]. For example, Lau and Lee [2] explored the effects of the thickness of a built-up printed circuit board (PCB) on the solder joint reliability of a WLCSP. In addition, the effects of design parameters such as die thickness and the kinds of solder material, have been extensively reported in the literature [2], [3]. However, the traditional WLCSP shows poor solder joint reliability during accelerated thermal cycling (ATC) tests. Therefore, proper structural designs of several different WLCSPs have been proposed in order to solve the reliability issue. Gonzalez et al. [4] introduced the concept of silicone under the bump (SUB) thereby creating the mechanical property of low module within the WLCSP so as to release the thermal stresses. Chang and Chiang [5] formed the Cu studs on the solder pads prior to the solder reflow process in order to substantially increase the strength of the solder joint itself. On the other hand, Chiang et al. [6] and Mercador et al. [7] found that solder joint reliability is highly dependent upon the geometry of the solder joint, such as the standoff height, lower/upper contact angles, solder volume, and solder joint profile. In order to obtain a better overall understanding of both the significance and the interaction effect of each factor as mentioned above, many systematic statistical approaches have been adopted to explore the relationship between design variables and the response. Vandevelde et al. [8] estimated the solder joint reliability of chip scale packaging by associating the FEA with DOE in order to obtain the parameter sensitivity. van Driel et al. [9] applied response surface models (RSMs) to determine the optimal settings of the product/process designs versus the possible failure mode of a vertical die crack within the typical die-attach packaging structure. However, none of these forgoing works gave any consideration to the WLCSP with stress compliant layer. And especially, none discussed the impacts and interactions of the upper/lower solder pad arrangements that have an influence on the fatigue life of the solder joint within the novel WLCSP, referred to as DL-WLCSP, and which is proposed in this present research.

The cross-sectional view of a DL-WLCSP is shown in Fig. 1. Two stress compliant layers are interposed between the silicon die and the solder joint array, to reduce the thermal deformation that resulted from a larger CTE mismatch of materials during temperature thermal loadings. The Rambus DRAM with 62 I/Os in area-arrayed format is taken as the test vehicle of DL-WLCSP (Fig. 2). With the purpose of protecting the internal solder joints, the total numbers of eight dummy solder joints, which are designed to be arranged in the corner areas of the packaging layout, can be considered as structural dummy supports with no electrical signals passing through them. The objectives of the present study include: (1) to predict the solder joint reliability by using a non-linear finite element analysis, including a 3D WLCSP model. In addition, validate the results of the experimental test by comparing them with the procedures of the FEA; and (2) to systematically present an effective design procedure for the prediction of solder joint reliability based on the application of the Central Composite Design, and followed by the analysis of the response sensitivity of the die-side and substrate-side pad diameters.