Circuit level prediction of device performance degradation due to negative bias temperature stress

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Abstract

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of IV characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.

Introduction

Negative bias temperature instability (NBTI) has been one of the most crucial reliability issues in the current ULSI circuit [1], [2]. Threshold voltage (Vth) shift and drain current (ID) reduction are the major degradations caused by the negative bias temperature stress (NBT stress) for pMOSFETs. These pMOSFETs degradations due to NBT stress may limit the total lifetime of the recent ULSI circuit by degrading the total circuit performances [2], [3], [4]. It is, then, necessary to predict the impact of degradations of pMOSFETs due to NBT stress that occurs during the operation of a circuit to its total performance at the circuit design stage of the manufacturing for reliable ULSI circuit production [5], [6], [7], [8], [9]. In this paper, we develop a prediction method of circuit performance degradation due to NBT stress by the circuit simulation level approach. For this purpose, an accurate model of pMOSFETs electrical degradation caused by the bias and temperature stress of an operation condition is primarily indispensable. Generally for modeling the electrical degradation by NBT stress, bias and temperature acceleration have been used for the experimental observation that employs stress conditions such as electrical field across the gate insulator (Ei) grater than 8 MV/cm and temperature (Temp.) higher than 398 K [10], [11], [12]. However, compared to the operation condition of which Ei = 4–8 MV/cm and Temp. up to around 398 K, bias and temperature acceleration induces much larger degradation to pMOSFETs’ electrical characteristics than that occurs in the operation condition and makes the predictions difficult [13], [14]. Then for the model development, we employed the cold hole injection method that accelerates only the degradation rate by injecting non-energetic cold holes into the inversion layer of stressed device without changing the magnitude of the degradation from that occurs in the operation condition [15], [16], [17]. Experimental results of the degradation in pMOSFET electrical characteristics are shown and the dominant degradation mechanism under operation condition is discussed in Section 2. Then in Section 3, Vth shift model and ID reduction model are developed based on the experimental observation. In Section 4, the developed models are implemented into a compact MOSFET model and the circuit level prediction of performance degradation is carried out using SPICE, and lastly its accuracy is verified with the experimental results of a stressed circuit’s performance.

Section snippets

Experimental results of pMOSFET degradation and degradation mechanism

A 130 nm CMOS technology is used to fabricate sample devices. The devices are fabricated on the p (epitaxial layer)/p+ substrate. The geometries of the devices are W/L = 10.0/10.0 and 10.0/0.13 μm and the gate insulator is 2.0 nm thick thermally oxidized pure SiO2. The operation voltage (VDD) of the sample devices is 1.2 V. Before addressing the experimental results, the employed cold hole injection method for degradation acceleration is briefly explained as follows [17]. The concept of this

Vth shift model

As shown in the previous section, the NBT stress induced degradations to pMOSFETs for the samples under the operation bias and temperature condition, that is our target of modeling, is dominated by hole trapping into the intrinsic defects. Then, Vth shift model is developed based on the previously reported charge trapping induced Vth shift model [17], [24]:ΔVth=qCoxDtrap-max1-exp-σ·γ·Qholeqβwhere, Dtrap−max, is the maximum trap density effectively active for a stress bias condition. σ and β are

Circuit level simulation and verification of performance degradation prediction

The developed models described in the previous section are implemented into a compact MOSFET model as follows [27]. Vth shift model is combined into the flat band voltage parameter, Vfb. This is because the Vth shift is caused by the flat band voltage shift due to the increased positive charge at and near the Si/insulator interface. And the mobility reduction model that is shown in Eq. (3) is combined into the term of the mobility that is limited by the coulomb scattering shown in the first

Conclusion

The advanced approach of predicting circuit performance degradation due to NBT stress is developed in this paper by accurately modeling the electrical degradation of pMOSFETs that occurs in the operation bias and temperature condition of circuits, and implementing the models into a compact MOSFET model. The developed models can directly link the electrical degradation of pMOSFETs to the degradation of total circuit performance through the circuit simulation, thus enable us to effectively design

Acknowledgements

The authors gratefully acknowledge Japanese Ministry of Economy, Trade and Industry and The New Energy and Industrial Technology Development Organization for their financial support.

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