Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs
Introduction
Nanoscale double gate (DG) and cylindrical gate-all-around (GAA) MOSFETs have been identified as strong candidates for replacing the conventional bulk MOSFET [19]. A major impetus for this advance is the improved gate control and the concomitant reduction in short-channel behavior for these device designs.
As an integral part of this development, precise compact models are needed for the DG and GAA MOSFET for implementation in circuit simulators and circuit design tools. To achieve the needed accuracy, the two-dimensionality of the potential and inversion charge distributions has to be taken into account. In the subthreshold regime of operation, the body electrostatics is dominated by the 2D capacitive coupling between the source, drain and gate electrodes. Laplace's equation for the DG MOSFET can be solved in different ways. One possibility is to perform a full Fourier expansion of the potential or by using a low-order truncation [4], [5], [12], [13], [19]. We have found conformal mapping to be particularly suitable for analyzing this regime analytically [2], [6], [8], [9], [10], [11], [14], [18]. This technique is briefly reviewed in Section 2. The GAA MOSFET, which is a 3D structure, cannot be analyzed directly by conformal mapping. Poisson's equation can be solved in cylindrical coordinates by means of a series expansion in Bessel functions [5]. However, here we show that the above analytical results from the DG structure can be applied to the GAA as well, by performing an appropriate compensation for the difference in gate control. In Section 2, modeling results for the DG and GAA MOSFETs are compared. The results are also verified by comparisons with numerical device simulations from Silvaco's Atlas device simulator.
In strong inversion, the electrostatics of the DG and the GAA MOSFET close to the channel barrier approach the long-channel behavior described in Refs. [7], [16], respectively. The potential distribution is then dominated by the inversion charge, allowing it to be self-consistently described by a 1D Poisson's equation in Cartesian (DG) or polar (GAA) coordinates. Strong inversion modeling results are compared and verified.
For the comparison and verification of the GAA and DG MOSFET models, we have assumed the following device specifications for both components [17]: gate length L = 25 nm, silicon substrate thickness (silicon string diameter for the GAA component) tsi = 12 nm, insulator thickness tox = 1.6 nm, relative dielectric permittivity of the insulator ɛox = 7.0, and p-type silicon body doping Na = 1015 cm−3. Idealized, equipotential drain and source Schottky contacts with work function 4.17 eV are used in order to facilitate the model verification against Atlas simulations, thus avoiding depletion regions in the contacts. As gate material, we selected a mid-gap metal with the work function 4.53 eV (corresponding to that of molybdenum).
Because of the short channel length of this device, the drain current will have the character of both drift-diffusion and ballistic transport, see Ref. [2]. However, here we only consider the drift-diffusion formalism.
Section snippets
Conformal mapping applied to DG MOSFET
The potential distribution owing to the capacitive coupling between the source, drain and gate contacts in the DG MOSFET can be obtained by solving the 2D Laplace equation by means of the conformal mapping technique. This solution then applies to the subthreshold regime, where the capacitive coupling dominates the electrostatics. The first step is to map the cross-section of the extended device body (see Fig. 1a), defined in the normal (x, y)-plane, into the upper half of a complex (u, i
Strong inversion electrostatics
In strong inversion, assuming that we can neglect the charge associated with the (low) doping density in the silicon body, Poisson's equation can be written aswhere φ(x, y) is the total electrostatic potential in the body accounting for both the electrons and the capacitive coupling between the electrodes, ni the intrinsic electron density, and Na is the acceptor doping density in silicon. For the DG MOSFET, m = 0, and for the GAA MOSFET, m
Drain current modeling
The small dimensions of the present devices indicate that the drain current will have the character of both drift-diffusion and ballistic/quasi-ballistic transport. Here, we discuss a drain current model based on the classical drift-diffusion formalism.
In the subthreshold regime the barrier topography is relatively rigid and is little affected by the drain current in both devices. This allows us to use the following simple, explicit drift-diffusion model for the current that relies on the shape
Conclusion
We have developed a precise, compact 2D model for calculating the electrostatics as well as drain current in nanoscale DG and GAA MOSFETs. The 2D modeling is based on conformal mapping techniques and a self-consistent analysis of the potential distribution, that include the effects of both the capacitive coupling between the contacts and the presence of electrons. Short-channel effects, including DIBL, are inherently contained in this analysis, and no adjustable parameters are used. The models
Acknowledgement
This work was supported by the European Commission under contract no. 506844 (SINANO) and the Norwegian Research Council under contract no. 159559/130 (SMIDA). We acknowledge the donation of TCAD tools from Silvaco and would like to thank Prof. Benjamin Iniguez from Universitat Rovira i Virgili, Spain for helpful discussions.
References (19)
- et al.
A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling
Solid State Electron.
(1996) - et al.
Scaling Theory for cylindrical fully depleted surrounding gate MOSFET
IEEE Electron. Device Lett.
(1997) - et al.
Precise 2D compact modeling of nanoscale DG MOSFETs based on conformal mapping techniques
- et al.
Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs
IEEE Trans. Electron. Device
(1993) - et al.
Generalized scale length for two-dimensional effects in MOSFETs
IEEE Electron. Device Lett.
(1998) - et al.
Two-dimensional analytical threshold voltage roll-off and subthreshold swing for undoped cylindrical gate all around MOSFET
Solid State Electron.
(2006) - et al.
Compact modeling solutions for double gate and gate-all-around MOSFETs
IEEE Trans. Electron. Device
(2006) - et al.
Explicit continuous model for long-channel undoped surrounding gate MOSFETs
IEEE Trans. Electron. Device
(2005) - et al.
2D modeling of nanoscale DG SOI MOSFETs in the subthreshold regime
J. Comput. Electron.
(2006)
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