A switched priority scheduling mechanism for ATM switches with multi-class output buffers

Abstract

In this paper, we propose a switched priority scheduling mechanism for an Asynchronous Transfer Mode (ATM) switch with multi-class output buffers. The switched priority scheduling mechanism is composed of a model-based linear controller, a heuristic nonlinear controller and the corresponding switching law of the controllers. The nonlinear controller is first applied to bring each class buffer into a small neighborhood of its operating point such that the linear controller can be used. The linear controller is then used to ensure that each buffer occupancy converges to its desired operating point. The service rate of each class buffer is periodically computed and dynamically adjusted. We derive the design formulae of the control mechanism such that each buffer occupancy globally converges to its desired operating point related to quality-of-service requirements.

Introduction

ATM technology is developed to integrate various services into future high-speed networks. It can support real-time service that allows users to transmit information with the guarantee of quality-of-service (QoS). To provide different types of service quality, ATM Forum has defined four classes of services for various traffic, namely Constant Bit Rate, Variable Bit Rate, available bit rate (ABR) and unspecified bit rate [4]. Among these, the ABR service is considered the best-effort traffic.

When traffic sources have equal priority and equivalent QoS requirements, a simple and high-speed scheduling method, first-in first-out (FIFO), is a proper solution. However, for packet-switching networks having a separate output buffer associated with each service class, some other scheduling algorithms, together with call admission control (CAC), are used to provide the guaranteed service to each class with various QoS requirements. Among these scheduling algorithms, Generalized Processor Sharing (GPS) algorithm and its varied versions have been designed to ensure fair bandwidth share of each class [7], [8]. Recently, Shim et al. [9] proposed a model-based priority scheduling algorithm for ATM switches with multi-class output buffers corresponding to each outgoing link. However, the method proposed in [9] can only be used at a neighborhood of the operating point. In practice, it is difficult to ensure that the initial state of each class buffer is in the neighborhood. This implies that this method cannot be globally used. Thus, it is necessary to design a simple algorithm, which can be globally used, to ensure QoS requirements of each class buffer. The major motivation of this paper is to present such a method.

As far as algorithms for ATM switches are designed, there generally exist two types of methods. One is heuristic [1], [3], [12] and the other is model-based [5], [2], [9]. The first method can be widely used. But there does not exist any mathematical analysis tool to strictly prove the convergence except some qualitative analysis tools to illustrate the trend. Thus, the performance cannot be rigorously analyzed, especially when the system is operated at a neighborhood of the corresponding operating point, and therefore it can only be demonstrated by a great number of simulations. Although the second method can be used to achieve the objectives and there exist many effective design methods when the system is at a neighborhood of the operating point [9], [5], [2], it is only possible to establish an exact model for a switch by using a fluid-flow traffic model [2]. To model the dynamics of a complex network, many restrictive requirements must be imposed on the network. These requirements limit the application of this method. Thus, this method can only be used for some ideal cases. Although these two methods have their own disadvantages, it is a nice idea to combine them together to design some effective algorithms.

In this paper, we propose a switched priority scheduling mechanism for an ATM switch with multi-class output buffers in which some ideas motivated from the control field are incorporated. The switched priority scheduling mechanism is composed of a model-based linear controller, a heuristic nonlinear controller and the corresponding switching law of the two controllers. Although the convergence speed of the linear controller is very fast, the linear controller can only work in a small vicinity of the operating point. Note that the nonlinear controller can globally bring the system to the vicinity of the operating point such that the linear controller can work. This implies that the switched controller can work globally. Moreover, the convergence speed of the nonlinear controller is very slow although it can be used globally. To improve the convergence speed, we use the switched controller rather than the nonlinear controller. Generally, the dynamics of each class buffer can only be modelled by a complex nonlinear model and there does not exist any effective method for the design of such a nonlinear model. However, a heuristic nonlinear controller can be designed. The heuristic nonlinear controller is first used to bring each class buffer into a small vicinity of its operating point, where the dynamic of the switch can be described by a linear model. A linear controller is designed based on the model and then used to ensure that each class buffer occupancy converges to its desired operating point related to QoS requirement [9]. Our switched mechanism can be used in the whole state space instead of only in the neighborhood of the operating point.

The remainder of the paper is organized as follows. The system models are described in detail in the following section. The switched priority scheduling mechanism is proposed in Section 3. Section 4 contains the analysis of the proposed mechanism. Its efficiency is illustrated through simulations in Section 5. Finally, some concluding remarks are given in Section 6.