Strategies for solving the Boolean satisfiability problem using binary decision diagrams

Abstract

The Boolean satisfiability (SAT) problem is the problem of finding a solution to the equation f=1, where f is a Boolean formula to be satisfied. Binary decision diagrams (BDDs) have been widely used to solve this problem; each of the individual output requirements of a multiple-output function is represented as a BDD and the conjunction of these requirements (product BDD) provides all satisfying solutions. However, these techniques suffer from BDD size explosion problems. This paper presents two BDD-based algorithms to solve the SAT problem that attempt to contain the growth of BDD size while identifying solutions quickly.

The first algorithm, called BSAT, is a recursive, backtracking algorithm that uses an exhaustive search to find a SAT solution. It exploits the well-known unate recursive paradigm to reduce the effective size of search space for the SAT problem. We recursively apply orthonormal expansion on highly binate functions that may eventually lead to unate cofactors. The second algorithm, called IS-USAT (for INCOMPLETE-SEARCH-USAT), incorporates an incomplete search to find a solution. The search is incomplete inasmuch as it is restricted to only those regions that have a high likelihood of containing the solution, discarding the rest. Using our techniques we were able to find SAT solutions not only for all MCNC and ISCAS benchmarks, but also for a variety of industry standard designs, solutions for many of which could not be found by contemporary BDD-based SAT techniques.

Introduction

The Boolean satisfiability problem (henceforth called SAT) is the problem of finding a solution to the equation f=1, where f is a Boolean formula to be satisfied. Formula f can be represented in conjunctive normal form (CNF), or by using binary decision diagrams (BDDs). Contemporary techniques that use BDDs to solve SAT suffer from size explosion problems. This paper presents strategies to solve the SAT problem efficiently using BDDs that attempt to contain the growth of BDD size.

The SAT problem has many direct applications in the electronic design automation (EDA) arena, which includes test pattern generation, timing analysis, logic verification, functional testing, etc. It belongs to the class of NP-complete problems with algorithmic solutions having exponential worst-case complexity [1]. This problem has been widely investigated, and continues to be so because efficient techniques can greatly impact the performance of satisfiability tools.

With respect to applications in VLSI-CAD, most instances of SAT formulations start from an abstract circuit description, for which a given circuit property (typically, value requirements at primary outputs) needs to be validated. The resulting formulation is then mapped onto an instance of SAT, often using CNF formulae. Classical approaches to SAT are based on variations of the well-known Davis and Putnam procedure [2]. Typical versions of the above [3], [4], [5], [6] incorporate a chronological backtrack-based search that, at each node in the search tree, selects an assignment and prunes subsequent search by iterative application of the unit clause and pure literal rules [7]. Recent approaches [8], [9] incorporate learning techniques and other conflict analysis procedures with non-chronological backtracks to prune the search space. In spite of these advances, CNF-SAT models and associated algorithms have several drawbacks which prompted us to consider other resources, namely, reduced ordered binary decision diagrams (ROBDDs) [10], [11].

If multiple instances of SAT need to be solved, mapping each problem description onto CNF-SAT can represent a large percentage of the total running time [5], [9]. This can create performance bottlenecks for other applications that rely extensively on information provided by SAT tools (e.g., ATPG [5], [6], equivalence checking [12], functional vector generation, etc.). Moreover, the requirement that the constraints be in CNF form leads to formulae with too many clauses [13]. The choice of ROBDDs was thus dictated not only by the issue of inter-operability of our SAT engines with various BDD-based verification/testing frameworks,¹ but also because of their compactness and their ease of manipulation.

Let us briefly describe the SAT problem as it appears in the context of our work and analyze the limitations of previous BDD-based solutions. Consider the circuit shown in Fig. 1. Given a set of output value requirements, say {u=1,v=1,w=1}, how do we find an input assignment that satisfies these requirements?

Building the product of the output Boolean functions for given output value requirements in terms of the primary inputs results in all satisfying solutions. Let f represent the product of the outputs, i.e.

$$\text{f=u·v·w=((a+b)·((a+b)·c+a}\text{b}\text{̄}\text{))·((a+b)·c+a}\text{b}\text{̄}\text{+d)=ac+bc+a}\text{b}\text{̄}\text{.}$$

It follows that any of the cubes ac, bc, or $\text{a}\text{b}\text{̄}$ provide the satisfying assignments. Similarly, if the output value requirements are {u=1,v=1,w=0}, then $\text{f=u·v·}\text{w}\text{̄}\text{=0}$, which implies that there is no SAT assignment for this instance.

Previous BDD-based SAT approaches [13], [14] model the overall constraints (i.e. conjunction of u,v,w) using a monolithic BDD. In such approaches, selecting any cube as a SAT solution amounts to traversing any path from the root node to the terminal vertex 1 [13], [14], [15]. While this simple formulation is appealing because it leverages the BDD manipulation algorithms, it is often the case that constructing and storing the product BDD f for large problems is not feasible. If the product f is large enough that it cannot be stored using a monolithic BDD, how do we find a satisfying assignment without attempting to construct such a prohibitively large product BDD? Solutions to this problem are the subject of this paper.

Using the BDD-based satisfiability techniques of [13], [14], [15] (termed BDD-SAT in this paper), we carried out a few experiments by constructing a BDD for the product of all output functions for the benchmark circuits. Experimental data are provided in Table 1. Such a straightforward approach performs well for a wide range of medium-sized circuits. However, for large circuits the conjunction operation is either too slow (benchmark C5315), or it results in a prohibitively large BDD that cannot be stored (des, 16×16 mult).

While carrying out these experiments, we made the following observation. While the end product BDD is generally quite small, the size of the intermediate products can be prohibitively large. For instance, the size of the end product BDD for the benchmark pair was just 7013 nodes. However, the size of the largest intermediate product was 382,493 nodes. This means that the intermediate products contain vast regions of empty solution space.

This issue of BDD size explosions of intermediate computations was also observed by Hu et al. in [16]. They proposed the idea of implicitly conjoined BDDs to reduce the size of intermediate computations by targeting the functionally dependent variables [17], a technique similar in flavor to that of partitioned BDDs [18]. The basic idea here was to represent a prohibitively large BDD as a conjunction of small BDDs represented in terms of intermediate variables. While these techniques [16], [17], [18] can be used to avoid BDD size blow-ups by using intermediate variables, the SAT solutions are ultimately required in terms of the primary input variables. Resolving these intermediate (dependent) variables in terms of the primary input (independent) variables again leads to BDD size explosion problems. Coudert and Madre in [19] contributed toward the use of image and pre-image computations in satisfiability and equivalence checking. Ranjan et al. [20] proposed extensions to Coudert's technique to efficiently solve the image and pre-image computation within a formal verification paradigm [21]. The techniques presented in [19] rely on iterative conjunction operations on the transition relations of the circuit, and as such are also plagued by excessive BDD size of intermediate image/pre-image products. While Ranjan et al. [20] present heuristics to partition and cluster the transition relations so as to be able to build their product, the success of their approach too has been rather limited.

As observed in [16], [18], and in the preliminary experiments by the authors of this paper, the presence of regions of empty solution space within the intermediate products is a significant cause of BDD size blow-up. Thus, in order to prevent BDD size explosion of intermediate computations, it becomes important to discard these regions of empty solution space from further consideration. This issue motivates the SAT techniques presented in this paper.

This paper presents a comprehensive infrastructure to efficiently solve the Boolean satisfiability problem using BDDs. In particular, two efficient search algorithms are presented. The algorithms exploit characteristics of unate functions in order to intelligently discard regions of the search space from further exploration, thus arresting the growth of BDD size. The first algorithm presented in this paper, called BSAT, is a recursive, backtracking algorithm to find a SAT solution. The well-known unate recursive paradigm [22], [23] is exploited to solve the SAT problem. We recursively apply orthonormal expansion on highly binate functions that may eventually lead to cofactors that are unate. Search for SAT solutions on the resulting unate cofactors can be efficiently performed. While the recursive paradigm has been successfully applied to various applications in logic synthesis, in the context of this paper, we demonstrate its effectiveness in solving the SAT problem efficiently, while controlling the growth of BDD size. While experiments over a wide range of benchmarks reveal that BSAT successfully arrests the growth of BDD size, because of the (semi-)exhaustive nature of search, it suffers from higher computation times. The second algorithm presented in this paper, called INCOMPLETE-SEARCH-USAT, attempts to overcome this deficiency.

INCOMPLETE-SEARCH-USAT (abbreviated as IS-USAT in the sequel) is an iterative, non-backtracking search algorithm to solve the SAT problem. The search is incomplete inasmuch as it is restricted to those regions that have a high likelihood of containing a solution, while discarding the rest. Storing a restricted search space in BDDs avoids BDD size explosion problems and further reduces the time of search. However, since only a part of the search space is explored, feasible SAT solutions that may exist only in unexplored regions cannot be found by this technique. We present a heuristic (based on the unateness properties of functions) that attempts to explore those regions of search space where there is a high chance of finding a solution. While this technique cannot be relied upon to prove unsatisfiability in unequivocal terms, we demonstrate with experiments that it is able to compute feasible SAT solutions quickly for a large number of SAT instances. Using the above SAT engines, we were able to find SAT solutions not only for all ISCAS'85 and MCNC benchmark circuits, but also for a variety of industry standard designs obtained from [24].

The paper is organized as follows. Section 2 covers preliminary concepts related to this paper. Section 3 describes characteristics of unate functions and their relationship to SAT solutions. In Section 4, we present a recursive, backtracking algorithm for SAT that exploits the properties of unate functions within the framework of the unate recursive paradigm. In Section 5, we present an iterative, non-backtracking search algorithm to solve the SAT problem. The achievements and limitations of these techniques are discussed and experimental results are analyzed. Section 6 concludes the paper.