Studies of mist deposited high-k dielectrics for MOS gates

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Abstract

This paper presents the results of the characterization of high-k dielectric films deposited by liquid source misted chemical deposition (LSMCD) in a cluster tool for advanced MOS gates. Electrical characterization (capacitance–voltage and current–voltage) was performed in conjunction with atomic force microscopy (AFM). The effects of in situ surface conditioning prior to deposition were also examined. Among processes investigated, the sequence depositing high-k dielectric, e.g. SrTa2O6, on nitrided oxide interlayer grown by a UV/NO process showed very good promise.

Introduction

In order to assure the required capacitance of the MOS gate stack in devices featuring geometries below 0.1 μm an extensive search for dielectrics with dielectric constant k higher than that of SiO2 (3.9) and other characteristics meeting the stringent requirements of MOS gates is currently underway. Among several compositions considered of prime interest are those which feature k higher than 15, are thermodynamically stable with silicon, can be obtained as low-leakage films in the 4–5 nm thickness regime, and maintain their structural integrity during post-deposition annealing cycles. A broad range of materials and deposition techniques is being explored to identify those producing gate dielectrics suitable for next generation CMOS devices.

The liquid source misted chemical deposition (LSMCD) method has been successfully employed in the deposition of low-k interlayer dielectrics [1] as well as high-k dielectrics for storage capacitors and ferroelectric RAMs (FRAMs) [2]. In this work we investigate electrical and material characteristics of high-k materials for MOS gates deposited using this method. The materials studied include ZrO2 and HfO2 as well as SrTa2O6 [3], [4].

Section snippets

Experimental

The LSMCD technique employs liquid metal-organic precursors as a source and deposits a controlled amount of liquid metal oxides in the form of sub-micron mist droplets onto the wafer surface at room temperature and atmospheric pressure [5]. The process is carried out in a nitrogen ambient and a high-voltage electrostatic field is used to control the deposition rate. In this study, the deposition runs were carried out in a commercial cluster (Fig. 1) consisting of a gas-phase surface

Results and discussion

In this investigation the promising results, equivalent oxide thickness (EOT)<1.5 nm, and Jg in the mA/cm2 range were obtained with HfO2 and ZrO2, (Fig. 2). However, these results were strongly dependent on the process conditions. The AFM characterization did show occasionally distorted surface morphology and localized discontinuity of surface coverage (Fig. 3a–b). In the case of Zr and Hf oxides and silicates these features were dependent on the concentration of the precursor and

Summary

Electrical and material characteristics of various high-k dielectrics deposited by LSMCD for MOS gates are investigated. Under proper process conditions both HfO2 and ZrO2 as well as SrTa2O6 films with adequate electrical and material characteristics can be obtained. Including a UV/NO gas-phase surface treatment prior to deposition results in an improvement in the electrical characteristics of the MOS gate stacks formed.

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