Room temperature plasma oxidation mechanism to obtain ultrathin silicon oxide and titanium oxide layers

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Abstract

Scaling rules for sub-micrometric MOS devices have led to the necessity of ultrathin dielectric films and high-k dielectric layers. In this paper we present first results of room temperature plasma oxidation to obtain ultrathin layers of SiO2 and TiO2. The oxidation process in O2 and N2O shows a power law dependence with time and inverse proportionality with pressure. The oxidation rate is inversely proportional to pressure for both high and medium resistivities substrates. An oxidation model is proposed to explain this behavior. Ellipsometric and CV characterization show complete oxidation of titanium verifying that a dielectric layer is formed.

Introduction

The continuous scaling down of the MOS transistors (TMOS), has lead to the necessity of ultrathin SiO2 layers with thickness below 3 nm. The presence of direct tunneling through these ultrathin layers has also led to intensive research of alternative or complementary dielectrics with high value of dielectric constant (high-k) to reduce the current density through these layers. Among technological challenges at this point, are to maintain the high quality of this ultrathin dielectric layers, as well as the good interface properties with the silicon substrate. Reduction of the temperature budget for dielectric formation is also required to provide the ultrashallow junctions needed for deep sub-micrometric devices. To fulfill these requirements several methods of ultrathin dielectric formation are been studied, as thermal oxidation in dry and diluted oxygen or N2O at temperatures about 850 °C or less [1], [2], [3], [4], rapid thermal oxidation process [5], [6] and more or less sophisticated deposition techniques [7], [8].

Plasma deposition techniques at temperatures around 400 °C are being used, where interface formation is done independently. The interface is formed by remote plasma oxidation of silicon at temperatures as low as 200 °C [7], [8]. Plasma oxidation has also been used as an alternative to obtain ultrathin and high quality SiO2 films at temperatures as low as 400 °C [9], [10], [11], [12], [13].

As transistor channel length continues reducing, scaling rules require that SiO2 layers also become thinner, and the values of gate current density become intolerated. For 100 nm channel length, the oxide thickness should be less than 1.5 nm and the current density passing through the dielectric is greater than 10 A/cm2 [14], [15]. The approach used to reduce the gate current is the use of high-k dielectric materials where a greater physical thickness Td can be used and still produce similar characteristics to a SiO2 gate TMOS having an equivalent SiO2 thickness Teq. The relation between Td and Teq is expressed byTeq=kSiO2kdTdkSiO2 is the dielectric constant of SiO2 and kd is the dielectric constant of the high-k dielectric.

This means that, when using a high-k dielectric, the real thickness of the dielectric Td can be kd/kSiO2 times greater than the required for SiO2 in order to follow scaling rules, leading to a reduction in the current, passing through the metal–insulator–semiconductor (MIS) structure. Several materials are being studied as alternative gate dielectrics, such as HfO2, ZrO2, Al2O3, Ta2O5, TiO2 and others, and several methods to obtain them are proposed [16], [17], [18], [19], [20], [21], [22], [23], [24], [25]. These high-k dielectrics must also have a difference in their conduction band energy with respect to the conduction band energy of the semiconductor (conduction band offset) higher than the maximum voltage value that will be applied to the transistor, which for this channel length is estimated around 1 V. This second condition is not accomplished by all the above mentioned dielectrics. To overcome this situation, a dielectric stack with a very thin SiO2 layer under the high-k dielectric can be used, with also the benefit of maintaining the good properties of the SiO2–Si interface. However the presence of the SiO2 film produces a strong reduction of the effective k. TiO2 films have values of k that can reach 100, depending on the method of obtaining it. However, its band offset is near to zero. For this last reason TiO2 layers are not recommended for single layer MOS structures but can be promising when used in stacks.

In this work we present first results of plasma oxidation at room temperature to obtain ultrathin SiO2 and TiO2 layers in barrel and parallel plate PECVD equipments in the presence of O2 and N2O as reactive gases. We report the growth kinetic observed and determine an empirical model for this oxidation procedure. Single layer and stacked TiO2–SiO2 MOS structures were fabricated and characterized using JV and CV curves.

Section snippets

Experiment

Three groups of experiments were performed on 6 Ω cm p-type (1 0 0) oriented (substrate type 1), 4000 Ω cm n-type (1 0 0) oriented (substrate type 2) and 0.1 Ω cm n-type (1 0 0) oriented silicon wafers (substrate type 3). Wafers of different doping concentration were used to study the oxidation kinetics. Substrates type 3 are also necessary to reduce series resistance in CV measurements, which can become critical for ultrathin structures.

Group 1: 6 Ω cm p-type silicon wafers (1 0 0) oriented and 4000 Ω cm

Oxidation mechanism

Fig. 1, Fig. 2 show curves of the SiO2 thickness vs. time, for 6 Ω cm p-type and 4000 Ω cm n-type samples respectively, for three different O2 pressures in a barrel equipment. As can be seen from these figures, the oxide thickness follows a power law with time, that can be expressed asX=αtn+X0α and n are adjusting parameters determined as the intercept and slope of the logarithmic plot of (XX0) vs. t, while X0 is the native oxide that remains after the HF cleaning procedure. This is not an

Conclusions

Ultrathin SiO2 and TiO2 layers were obtained by plasma oxidation of silicon and titanium at room temperature. A model for silicon oxidation kinetics, following a power law with time, represents well the obtained behavior. Parameter α is inversely proportional to pressure for high and medium resistivities substrates. Parameter n showed no pressure or substrate dependence, but varies with the oxidation gas. The limiting mechanism in the silicon oxidation is the gas transport mechanism.

During

Acknowledgements

We want to thank Olga Gallegos and Enriqueta Aguilar for sample preparation, Maricela Flores for electrical characterizations and to M. Sc. Rogelio Fragoso for Atomic Force Microcopies.

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