A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization

doi:10.1016/S0026-2714(02)00295-0

Microelectronics Reliability

Volume 43, Issue 1, January 2003, Pages 17-41

https://doi.org/10.1016/S0026-2714(02)00295-0 Get rights and content

Abstract

In this paper the basic techniques for defect isolation and visualization used in physical failure analysis of trench technique dynamic random access memories (DRAMs) are reviewed. The methods described are state-of-the-art for DRAM failure analysis down to 0.14 μm feature size and beyond. In addition to defect isolation and defect visualization from the front side of a die, the backside preparation approach is reviewed. Beginning with basic sample preparation techniques including mechanical polishing, wet and dry etching and focused ion beam (FIB) applications advantages and disadvantages of various techniques are discussed. In the second section of the paper different types of optical microscopes are covered as well as scanning and transmission electron microscopes. The imaging capabilities of the FIB systems are included in this section. Finally, some applications of scanning probe techniques especially for dopant measurements and thin oxide characterization are described.

Introduction

The failure analysis (FA) process starts with electrical characterization of the failure. The more accurately the electrical measurements can localize the fail in the circuitry of the chip, the higher is the success rate for a following destructive, physical analysis. Besides electrical analysis, other non-destructive methods, e.g., emission microscopy, are available to localize the electrical fail to a physical location on the chip. A summary of methods to localize a defect is given by Benstetter et al. [1].

After the non-destructive pre-localization of a failure, a subsequent delayering of the chip is performed to determine the root cause of the electrical failure. A generic cross-section of a dynamic random access memory (DRAM) chip is given in Fig. 1 [1]. Physical failure analysis (PFA) reverses the production process by subsequently removing the different layers of the chip. In Fig. 2, a flow chart demonstrates the sequence of decapsulation and deprocessing steps with corresponding inspection and analysis procedures. The electrical pre-characterization of the fail and the experience of the FA engineer determine the specific analysis method for a failing chip. Griep et al. [2] report the use of defect simulation to determine the best preparation procedure for a given electrical fail signature, following a general trend towards computer-based expert systems.

Section snippets

Defect isolation: preparation methods

A major part of PFA is the deprocessing of the integrated structure in order to isolate physical defects [3]. Four major techniques are available:

•
mechanical polishing,
•
wet chemical etching,
•
plasma etching,
•
focused ion beam (FIB) milling.

The following chapters will describe the main applications and the advantages/disadvantages of the different techniques. Examples will be given for applications. The choice of the deprocessing method is based on electrical and process data, which often narrow

Backside preparation approach

The recently developed new packaging types such as flip-chip and lead-on-chip dies, together with the increasing number of metal layers, initiated a focus on backside analysis. Driven by the new packaging types the application of backside deprocessing spread fast and became an alternative to be considered for most FA analysis. The main new challenge for this approach is to remove the bulk silicon. Further analysis is then performed using all the methods described earlier in 2 Defect isolation:

Summary

This paper reviews the basic techniques for defect isolation and visualization used in PFA of trench technique DRAMs. The basic sample preparation techniques including mechanical polishing, wet and dry etching and FIB applications are discussed with their advantages and disadvantages. Examples show some typical application for these different techniques. The second section of the paper describes the basic defect visualization techniques. Different types of optical microscopes are covered as

Acknowledgements

The authors are grateful to Carole Graas (Infineon Technologies) for reviewing this paper and her constructive inputs. The authors thank Loren Hahn and Joe Myers for their help with all FIB related issues, Rick Kontra and Christy Johnson for performing the TEM work and their critical review of the respective part of this paper. Further, Phil Kazuba and Leon Moszkowicz for performing the AFM and SCM work and their input for this paper on this subject. Ron Danyew, Tim Pollock, Bob Latimer and

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Citation Excerpt :
The long excitation wavelength of 2PE also leads to a significant reduction of unwanted optical scattering when an intervening scattering medium is present along the path of the propagating focused beam [7]. The decrease in scattered excitation light is highly desirable when imaging through the backside of high-density multilayer IC samples where the probe beam has to pass through a layer (∼1 μm thick) of bulk Silicon material that exists before the active region where the circuit is located [8,9]. The high acquisition and maintenance costs of a femtosecond pulsed laser have prevented the adoption of 2P-OBIC as a standard failure analysis tool in the semiconductor industry.
Optical-beam induced current (OBIC) is generated in blue light-emitting diode samples (peak emission wavelength = 480 nm) via two-color (two-photon) excitation using the second- (502.9 nm) and third-order (635.9 nm) Stokes beam outputs of a hydrogen Raman shifter that is pumped by the 355 nm pulsed output (5.4 ns pulsewidth) of a 10 Hz Nd:YAG laser. Two-color OBIC generation happens only in sample regions where the two focused Stokes beams overlap in both space and time. We have verified the direct proportionality of the two-color OBIC signal with the product of the individual Stokes beam intensities as well as the localized nature of two-color OBIC generation in the common focal volume of the two confocal excitation beams.
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As charge tunnelling through thin and ultra-thin silicon dioxide layers is regarded as the driving force for MOS device degradation the determination and characterisation of electrically week spots is of paramount importance for device reliability and failure analysis. Conductive atomic force microscopy (C-AFM) is able to address this issue with a spatial resolution smaller than the expected breakdown spot. For the determination of the electrically active oxide thickness in practice an easy to use model with sufficient accuracy and which is largely independent of the oxide thickness is required. In this work a simplified method is presented that meets these demands. The electrically active oxide thickness is determined by matching of C-AFM voltage–current curves and a tunnelling current model, which is based on an analytical tunnelling current approximation. The model holds for both the Fowler–Nordheim tunnelling and the direct tunnelling regime with one single tunnelling parameter set. The results show good agreement with macroscopic measurements for gate voltages larger than approximately 0.5–1 V, and with microscopic C-AFM measurements. For this reason arbitrary oxides in the DT and the FNT regime may be analysed with high lateral resolution by C-AFM, without the need of a preselection of the tunnelling regime to be addressed.
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²: Formerly Siemens Components.

¹: DRAM Development Alliance IBM/Infineon, IBM Semiconductor Research and Development Center.

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Introductory Invited PaperA review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization

Abstract

Introduction

Section snippets

Defect isolation: preparation methods

Backside preparation approach

Summary

Acknowledgements

Microelectron. Reliab.

Microelectron. Reliab.

Thin Solid Films

J. Non-Cryst. Solids

Appl. Surf. Sci.

Microelectron. Reliab.

Application of defect simulation as a tool for more efficient failure analysis

Qual. Reliab. Eng. Int.

Praeparationstechniken fuer die Fehleranalyse an integrierten Halbleiterschaltungen

The science and engineering of microelectronic fabrication

Failure analysis preparation: a system assessment

Semicond. Int.

Focused ion beam induced gas etching

Jpn. J. Appl. Phys. 1

Advanced FIB applications for product analysis

Confocal microscopy

Confocal scanning tackles submicron inspection

Eur. Semicond.

Optics

Failure mode analysis of a 0.25 μm CMOS technology by scanning electron and ion beam

Solid State Phenom.

Gate oxide defect analysis using scanning electron microscopy (SEM)/metal oxide semiconductor (MOS)/electron beam induced current (EBIC) with subnano ampere current breakdown

Solid State Phenom.

Detailed investigation of SEM-results by TEM at one sample using FIB-technique

Microelectron. Reliab.

The materials science of thin films

Reliability and failure of electronic materials and devices

Transmission electron microscopy: a review and a comparison with high resolution scanning electron microscopy

Transmission electron microscopy of silicon VLSI circuits and structures

Semiconductor measurements and instrumentation

Imaging gate oxide ruptures

Introductory Invited Paper
A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization