Low frequency noise in 0.12 μm partially and fully depleted SOI technology

Abstract

Low frequency noise characterization of 0.12 μm silicon-on-insulator (SOI) CMOS technology is for the first time performed for partially and fully depleted N-MOSFETs. Static performances of the experimental devices are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we point out an enhancement of the extracted trap densities for both architectures compared to previously obtained results in 0.25 μm SOI CMOS technology. As regards drain current spectral densities in saturation mode, we notice some peculiarities occurring for the Kink-related excess noise.

Introduction

Silicon-on-insulator (SOI) devices have shown over the last past years promising advantages over the Si bulk technology, especially for low power/low voltage integrated circuits due to significantly improved electrical properties such as increased driving current, lower parasitic source/drain capacitances and total dielectric isolation. Two device architectures have consequently gained a growing interest beside semiconductor suppliers: fully depleted (FD) and partially depleted (PD) MOSFETs which both present some special peculiarities [1], [2], [3] due to the presence of a buried oxide layer. As far as PD devices are concerned, they exhibit floating body effects such as the Kink effect, parasitic bipolar transistor, etc… Indeed, the neutral zone within the silicon film attracts holes issued from the impact ionization occurring at the drain edge, and the body potential consequently increases, which contributes to a decrease of the threshold voltage, and a drain current increase (Kink effect). If the body potential is large enough, the source-to-body junction is forward biased, activating the parasitic bipolar transistor action. Regarding the FD architecture, the most relevant point to figure out is the interface coupling effects between the front and back gates due to a reduced silicon film thickness (30 nm in this study). This means that the electrical properties (such as the threshold voltage, the subthreshold slope…) at one interface are dependent from the applied biases at the opposite interface [4].

Low frequency noise analysis in MOSFETs is a relevant characterization tool, and provides pertinent information about the maturity level and the evaluation of a given technology. Shrinking MOS devices to very deep-submicron dimensions, an increase of the overall 1/f noise may alter device performances in terms of analogue or digital circuit applications, and needs to be investigated. Up to now, 1/f noise on 0.25 μm SOI N-MOSFETs has been extensively studied in the literature for both PD and FD architectures [5], [6], but, to our knowledge, only a few results [7] have been already reported on 0.12 μm PD SOI CMOS technology. Nevertheless, this is a rather important study to carry out, in order to see if the existing noise models [8] are still suitable, and to evaluate the impact of scaling down on low frequency noise levels.

After having considered the transfer and output characteristics, we present the normalized drain current power spectral densities in the linear regime (V_d=50 mV) for both PD and FD N-MOSFETs. Then, in the saturation regime, we focus on the presence or absence of the conventional Kink-related excess noise for PD devices, whereas we also show the appearance of a Kink excess noise for FD devices, already observed in 0.25 μm moderately FD N-MOSFETs [9], but for higher frequencies.