In-situ metrology and testing of nanotwinned copper pillars for potential air gap applications

doi:10.1016/j.mee.2010.04.019

Microelectronic Engineering

Volume 87, Issue 11, November 2010, Pages 2046-2049

https://doi.org/10.1016/j.mee.2010.04.019 Get rights and content

Abstract

We have performed in-situ nanocompression testing in a transmission electron microscope (TEM) of copper pillars having dimensions of the same order of typical via and line structures used in the semiconductor industry. We show direct evidence that twin boundaries can withstand extensive plastic deformation and still retain their structure when compared to regular grain boundaries. Through real-time TEM observations we have verified the deformation mechanisms of twin boundaries predicted by molecular dynamic (MD) simulations. Our quantitative in-situ stress measurements are also in close agreement with those reported by MD and energetics based calculations.

Introduction

Copper is widely used in interconnect technology due to its superior electrical properties as compared to aluminium. Currently, the integration of ultra low K materials with copper interconnects beyond the 45 nm node [1] poses a significant challenge due to the low hardness and mechanical stability of the ultra low K materials and the problems that arise from this during the etching and stripping processes in microelectronic fabrication [2]. Therefore, localized integration of “air gaps” may be the only viable solution to achieve dielectric constants below 2.0 and also keep up with the International Technology Road Map for semiconductors [3]. Considerable research effort has been directed towards integrating air gap structures by non-conformal chemical vapor deposition (CVD) process or by using sacrificial materials [4]. A major concern from the introduction of air gaps in interconnects is the overall mechanical integrity of the stack [5]. During packaging the upper layers of interconnects are in close proximity to the packaging materials and experience considerable stress gradients [6]. The load carrying capacities of the vias and lines become particularly important when air gap technology is used [7]. It is not known experimentally if the vias and lines will be able to withstand the processing stresses resulting in various packaging technologies that will be used in conjunction with air gap technology. Thus, there is a need to be able to measure the mechanical strength of Cu vias and lines to understand the deformation characteristics and evaluate the mechanical stability of isolated structures as electronic devices become smaller.

Section snippets

Experimental

Uchic et al. has developed a new method to measure the mechanical properties of individual structures at small scales [8]. The method involves the preparation of sub-micron sized pillars by Focused Ion Beam (FIB) and testing them under uniaxial compression. This method has been extended to electron transparent range by Shan et al. [9]. The dimensions of the pillars are very similar to the typical via structures used in higher levels of metallization layer for integrated circuits. Therefore,

Results and discussion

Compression of the pillars were performed at a displacement rate of 10 nm/s and limited to a maximum depth of 100 nm. Experiments were carried out under displacement control, since this mode has been known to show greater sensitivity to transient phenomena involving dislocation events such as nucleation and transmission [11]. Fig. 3(a) shows the engineering stress vs displacement curve for the pillar. The initial part of the stress-displacement curve demonstrates an elastic response followed by a

Conclusion

In summary, our in-situ nanocompression experiments provided a method to directly measure the yield stress of Cu pillars which are similar in dimension to “air gap” type interconnects used in advanced microelectronics. Twin boundaries have been shown to withstand extensive plastic deformation, and the deformation mechanisms at the nanotwinned boundaries verify the processes described by previous MD simulations.

Acknowledgements

This work is supported by NSF/NIRT-0506841: “Nanostructured Materials for Interconnect and Packaging Technology”, Dr. Ken Chong is the program monitor. Research at the National Center for Electron Microscopy was supported by the Scientific User Facilities Division of the Office of Basic Energy Sciences, U.S. Department of Energy under Contract # DE-AC02-05CH11231.

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In-situ metrology and testing of nanotwinned copper pillars for potential air gap applications

Abstract

Introduction

Section snippets

Experimental

Results and discussion

Conclusion

Acknowledgements

Microelectron. Eng.

Microelectron. Eng.

Microelectron. Eng.

Microelectron. Eng.

Acta Mater.

Scripta Mater.

Scripta Mater.

Acta. Metall. Mater.

Analysis of flip-chip packaging challenges on copper/low-k interconnects

IEEE Trans. Device Mater. Res.