Evaluation of cube and data manipulator networks☆
References (49)
- et al.
On the number of permutations performable by the augmented data manipulator network
IEEE Trans. Comput.
(Apr. 1982) - et al.
The extra stage cube: A fault-tolerant interconnection network for supersystems
IEEE Trans. Comput.
(May 1982) - et al.
The use of 4 x 4 switching elements in the multistage cube networks
Testing and fault-tolerance of multistage interconnection networks
Computer
(Apr. 1982)Graph theoretical analysis and design of multistage interconnection networks
IEEE Trans. Comput.
(July 1983)- et al.
Computer interconnection structures: Taxonomy, characteristics, and examples
ACM Comput. Surveys
(Dec. 1975) - et al.
Design and validation of a connection network for many-processor multiprocessor systems
Computer
(Dec. 1981) STARAN parallel processor system hardware
The flip network in STARAN
- et al.
PUMPS architecture for pattern analysis and image data-base management
IEEE Trans. Comput.
(Oct. 1982)
Modular interconnection networks with asynchronous control
A fault-tolerant connecting network for multiprocessor systems
X-tree: A tree structured multi-processor computer architecture
Analysis and simulation of buffered delta networks
IEEE Trans. Comput.
(Apr. 1981)
Data manipulating functions in parallel processors and their implementations
IEEE Trans. Comput.
(Mar. 1974)
A survey of interconnection networks
Computer
(Dec. 1981)
Fault-diagnosis for a class of multistage interconnection networks
IEEE Trans. Comput.
(Oct. 1981)
Very high-speed computing systems
Banyan networks for partitioning multiprocessor systems
A control processor for a reconfigurable array computer
A shuffle-exchange network with simplified control
IEEE Trans. Comput.
(Jan. 1976)
Access and alignment of data in an array processor
IEEE Trans. Comput.
(Dec. 1975)
A description method of interconnection networks
IEEE Tech. Committee Distrib. Process. Quart.
(Feb. 1981)
The advanced data processing test bed
Cited by (6)
Interconnection network analysis for a compliant massively parallel processor
1997, Journal of Systems ArchitectureDestination Tag Routing Techniques Based on a State Model for the IADM Network
1992, IEEE Transactions on ComputersEliminating Memory Fragmentation within Partitionable SIMD/SPMD Machines
1991, IEEE Transactions on Parallel and Distributed SystemsDesign and Analysis of Dynamic Redundancy Networks
1988, IEEE Transactions on ComputersCommunication techniques in parallel processing
1988, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)An introduction to the multistage cube family of interconnection networks
1987, The Journal of Supercomputing
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This work was supported by the United States Army Research Office, Department of the Army, under Grant DAAG29-82-K-0101; the National Science Foundation under Grant ECS 80-I6580; and the Air Force Office of Scientific Research, Air Force Systems Commands, USAF, under Grant AFOSR-78-3581. The U.S. Government's right to retain a nonexclusive royalty-free license in and to this paper, for governmental purposes, is acknowledged.
Copyright © 1985 Published by Elsevier Inc.