Abstract
A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667/800/1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG). To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps-1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm2.
概要
创新点
本文提出了一种适用于DDR3应用新的低功耗, 面积高效的全数字延迟锁定环电路. 全数字延迟锁相环通过使用相位检测器, 延迟控制延迟线, 数字环路滤波器控制器和延迟发生器, 可以处理的输入时钟频率范围从333 MHz 到800 MHz (DDR3-1600). 为了实现1.6 Gb/s/pin 的操作, 采用一种新型DCDL 方案. 该DCDL 具有以并联电容器为基础的数字控制的延迟元件, 所以延迟时间比较短. 一个分程控制温度计码发生器生成的控制电压, 用来设置一个在电流受控反相器的电流. 在40-nm CMOS 工艺制造的测试芯片给出667 Mbps-1.6 Gbps 的数据速率. 实验结果表明, 在1.1 V 操作电压下功耗为1.87 mW, 有效面积为0.0137 mm2.
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Chen, H., Ma, S., Wang, L. et al. A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller. Sci. China Inf. Sci. 57, 1–8 (2014). https://doi.org/10.1007/s11432-014-5226-1
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DOI: https://doi.org/10.1007/s11432-014-5226-1
Keywords
- all-digital delay-locked loop
- double-data-rate
- digitally controlled delay line
- shunt capacitor
- thermometer code