Abstract
As feature size scales down, reliability issues like single event upset (SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.
Similar content being viewed by others
References
International technology roadmap for semiconductors. http://www.itrs.net/. July 2010
Rockett L R. Designing CMOS data cells for space systems. Microelectron J, 2004, 35: 953–967
Tang D, Li Y H, Zhang G H, et al. Single event upset sensitivity of 45 nm FDSOI and SOI FinFET SRAM. Sci China Tech Sci, 2013, 56: 780–785
Omaña M, Rossi D, Metra C. Latch susceptibility to transient faults and new hardening approach. IEEE T Comput, 2007, 56: 1255–1268
Nan H, Choi K. Low cost and highly reliable hardened latch design for nanoscale CMOS technology. Microelectron Reliab, 2012, 52: 1209–1214
Huang P C, Chen S M, Liang Z F, et al. Mirror image: Newfangled cell-level layout technique for single-event transient mitigation. Chin Sci Bull, 2014, 59: 2850–2858
Qin J R, Li D W, Chen S M. A novel layout for single event upset mitigation in advanced CMOS SRAM cells. Sci China Tech Sci, 2013, 56: 143–147
Ochoa A, Axness C L, Weaver H T, et al. A proposed new structure for SEU immunity in SRAM employing drain resistance. IEEE Electr Device L, 1987, 8: 537–539
Shiyanovskii Y, Wolff F, Papachristou C. SRAM cell design protected from SEU upsets. In: 14th IEEE International On-Line Testing Symposium, Catalunya, Spain, 2008. 169–170
Whitaker S, Canaris J, Liu K. SEU hardened memory cells for a CCSDS Reed-Solomon encoder. IEEE T Nucl Sci, 1991, 38: 1471–1477
Zhang G, Shao J, Liang F, et al. A novel single event upset hardened CMOS SRAM cell. IEICE Electronics Express, 2012, 9: 140–145
Jahinuzzaman S M, Rennie D J, Sachdev M. A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE T Nucl Sci, 2009, 56: 3768–3773
Rockett L R. An SEU-hardened CMOS data latch design. IEEE T Nucl Sci, 1988, 35: 1682–1687
Sarkar S, Adak A, Singh V, et al. SEU tolerant SRAM cell. In: IEEE 12th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA USA, 2011. 1–6
Shayan M, Singh V, Singh A D, et al. SEU tolerant robust memory cell design. In: IEEE 18th International On-Line Testing Symposium, 2012. 13–18
Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology. IEEE T Nucl Sci, 1996, 43: 2874–2878
D’Alessio M, Ottavi M, Lombardi F. Design of a nanometric CMOS memory cell for hardening to a single event with a multiple node upset. IEEE T Device Mater Reliab, 2014, 14: 127–132
Qin J R, Chen S M, Liu B W, et al. Research on single event transient pulse quenching effect in 90 nm CMOS technology. Sci China Tech Sci, 2011, 54: 3064–3069
Geng C, Liu J, Zhang Z G, et al. Monte Carlo simulation based on Geant4 of single event upset induced by heavy ions. Sci China-Phys Mech Astron, 2013, 56: 1120–1125
Geng C, Xi K, Liu J, et al. Simulation of the characteristics of low-energy proton induced single event upset. Sci China-Phys Mech Astron 2014, 57: 1902–1906
Garg R, Li P, Khatri S P. Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs). In: IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, 2008. 1788–1791
Garg R, Jayakumar N, Khatri S P, et al. Circuit-level design approaches for radiation-hard digital electronics. IEEE T Vlsi Syst, 2009, 17: 781–792
Wey I, Yang Y S, Wu B C, et al. A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron J, 2014, 45: 1–13
Rockett L R. Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors. IEEE T Nucl Sci, 1992, 39:1532–1541
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Wang, L., Zhang, G., Zeng, Y. et al. Low power and high write speed SEU tolerant SRAM data cell design. Sci. China Technol. Sci. 58, 1983–1988 (2015). https://doi.org/10.1007/s11431-015-5929-6
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11431-015-5929-6