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Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

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Abstract

Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.

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Authors and Affiliations

  1. Software College, Northeastern University, Shenyang, 110819, China

    Ji-Liang Zhang & Xing-Wei Wang

  2. College of Information Science and Engineering, Hunan University, Changsha, 410082, China

    Qiang Wu

  3. School of Physics and Electronics, Central South University, Changsha, 410083, China

    Yi-Peng Ding

  4. Research Institute of Information Technology, Tsinghua University, Beijing, 100084, China

    Yong-Qiang Lv & Qiang Zhou

  5. School of Computer and Software, Nanjing University of Information Science and Technology, Nanjing, 210044, China

    Zhi-Hua Xia & Xing-Ming Sun

Authors
  1. Ji-Liang Zhang
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  2. Qiang Wu
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  3. Yi-Peng Ding
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  4. Yong-Qiang Lv
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  5. Qiang Zhou
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  6. Zhi-Hua Xia
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Corresponding author

Correspondence to Xing-Wei Wang.

Additional information

This work was supported in part by the National Science Foundation for Distinguished Young Scholars of China under Grant No. 61225012, the National Natural Science Foundation of China under Grant Nos. 61572123, 61501525, 61402162, 61232016, and U1405254, Hunan Province Science and Technology Project under Grant No. 2014RS4033, and the PAPD fund.

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Zhang, JL., Wu, Q., Ding, YP. et al. Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function. J. Comput. Sci. Technol. 31, 124–136 (2016). https://doi.org/10.1007/s11390-016-1616-8

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  • DOI: https://doi.org/10.1007/s11390-016-1616-8

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