Abstract
In the part 2 of advanced Audio Video coding Standard (AVS-P2), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, symmetric matching, quarter precision interpolation, etc. However, these new features enormously increase the computational complexity and the memory bandwidth requirement, which make motion compensation a difficult component in the implementation of the AVS HDTV decoder. This paper proposes an efficient motion compensation architecture for AVS-P2 video standard up to the Level 6.2 of the Jizhun Profile. It has a macroblock-level pipelined structure which consists of MV predictor unit, reference fetch unit and pixel interpolation unit. The proposed architecture exploits the parallelism in the AVS motion compensation algorithm to accelerate the speed of operations and uses the dedicated design to optimize the memory access. And it has been integrated in a prototype chip which is fabricated with TSMC 0.18-μm CMOS technology, and the experimental results show that this architecture can achieve the real time AVS-P2 decoding for the HDTV 1080i (1920× 1088 4:2:0 60field/s) video. The efficient design can work at the frequency of 148.5MHz and the total gate count is about 225K.
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Supported by the National High Technology Development 863 Program of China under Grant No.2003AA1Z1290.
Jun-Hao Zheng received the B.S. degree (June 2000) and M.S. degree (June 2003) both from Huazhong University of Science and Technology, Wuhan, China. Now he is working toward the Ph.D. degree in the Dept. Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences. His major research interests include video coding technology and associated VLSI architectures.
Lei Deng received his B.Sc. degree in computer science, in 1998 from Jilin University and M.Sc. degree in computer science and engineering, in 2000 from Harbin Institute of technology. He is pursuing his Ph.D. degree in the Harbin Institute of Technology for computer architecture and video signal processing. His research interests lie in the areas of computer architecture, digital signal processing and video compression.
Peng Zhang received the B.S. degree in electronic engineering and information science from University of Science and Technology of China, in 2002, and the M.S. degree in computer science from Institute of Computing Technology, Chinese Academy of Sciences, in 2004. At present, he is a Ph.D. candidate in Institute of Computing Technology, Chinese Academy of Sciences. His research interests include video coding, computer architecture, effective VLSI implementation and SoC design.
Don Xie received the M.S. and the Ph.D. degrees in electrical engineering from University of Rochester, New York, USA in 1992 and 1994, respectively. Now he is the engineering director of the Grandview Semiconductor, Beijing, China. His research interests include the SoC design and embedded system for consumer electronics.
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Zheng, JH., Deng, L., Zhang, P. et al. An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder. J Comput Sci Technol 21, 370–377 (2006). https://doi.org/10.1007/s11390-006-0370-8
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DOI: https://doi.org/10.1007/s11390-006-0370-8