Energy-efficient scheduling with individual packet delay constraints over a fading channel

Abstract

This article focuses on energy-efficient packet transmission with individual packet delay constraints over a fading channel. The problem of optimal offline scheduling (vis-à-vis total transmission energy), assuming information of all packet arrivals and channel states before scheduling, is formulated as a convex optimization problem with linear constraints. The optimality conditions are analyzed. From the analysis, a recursive algorithm is developed to search for the optimal offline scheduling. The optimal offline scheduler tries to equalize the energy-rate derivative function as much as possible subject to causality and delay constraints, in contrast to the equalization of transmission rates for optimal scheduling in static channels. It is shown that the optimal offline schedulers for fading and static channels have a similar symmetry property. Combining the symmetry property with potential idling periods, upper and lower bounds on the average packet delay are derived. The properties of the optimal offline schedule and the impact of packet sizes, individual delay constraints, and channel variations are demonstrated via simulations. A heuristic online scheduling algorithm, assuming causal traffic and channel information, is proposed and shown via simulations to achieve energy and delay performances comparable to those of the optimal offline scheduler in a wide range of scenarios.

Appendices

Appendix A: Uniqueness of optimal offline schedule

The uniqueness of the optimal offline schedule can be proved by contradiction. First, a transmission rate vector $\vec{r}$ is said to be feasible if it satisfies all the four constraints in (1). Because these constraints are all linear, it is easy to see that the set of all feasible vectors is convex. That is, a convex combination of two feasible vectors yields another feasible vector. Now suppose there are two distinct optimal rate vectors

$$\vec{r}^{(1)}=[r_1^{(1)},\ldots,r_{M+D-1}^{(1)}]$$

and

$$\vec{r}^{(2)}=[r_1^{(2)},\ldots,r_{M+D-1}^{(2)}].$$

Define

$$\vec{r}^{(3)}=\delta\vec{r}^{(1)}+(1-\delta)\vec{r}^{(2)},\,\, 0 < \delta < 1.$$

Obviously, $\vec{r}^{(3)}$ is feasible. Since f(r _i ,g _i ) is a strictly convex function of r _i for any $i\in[1,\ldots,M+D-1],$ we have

$$f(r^{(3)}_i,g_i)\,\le\,\delta f(r^{(1)}_i,g_i)+(1-\delta)f(r^{(2)}_i,g_i),$$

where the equality holds if and only if $r^{(1)}_i=r^{(2)}_i.$ Since $\vec{r}^{(1)}\neq \vec{r}^{(2)},$ there exists at least one $j\in[1,\ldots,M+D-1]$ such that $r^{(1)}_j\neq r^{(2)}_j,$ and consequently,

$$\sum_{i=1}^{M+D-1}f(r^{(3)}_i,g_i) < e_{opt},$$

where

$$e_{opt}\,\triangleq\,\sum_{i=1}^{M+D-1}f(r^{(1)}_i,g_i)=\sum_{i=1}^{M+D-1}f(r^{(2)}_i,g_i).$$

Thus, $\vec{r}^{(3)}$ is strictly more energy-efficient than the two optimal rate vectors $\vec{r}^{(1)}$ and $\vec{r}^{(2)},$ which causes a contradiction.

Appendix B: Additional complementary slackness conditions

This is to prove the additional complementary slackness conditions in (5) for the optimal offline schedule. Recall that:

• (1) $h_{l,m}(\vec{r}^{\ast}) < 0$ implies that $\mu_{l,m}^{\ast}=0;$

• (2) $\mu_{l,m}^{\ast} > 0$ implies that $h_{l,m}(\vec{r}^{\ast}) =0,$

for any l and m, due to the conventional complementary slack condition by (4).

The first condition, $\mu_{1,m}^{\ast} \mu_{3,m}^{\ast}=0, m=1,\ldots,M,$ is due to the fact that given $B_m > 0, m=1,\ldots,M,$ if $\mu_{3,m}^{\ast} > 0$ (hence $h_{3,m}(\vec{r}^{\ast})= -r_m^{\ast} = 0$ and so slot m is an idle slot), we have

$$ \begin{array}{lll} h_{1,m}(\vec{r}^{\ast}) & =\sum_{i=1}^{m} r_i^{\ast}\tau_s - \sum_{i=1}^{m} B_i \\ & =\sum_{i=1}^{m-1} r_i^{\ast}\tau_s - \sum_{i=1}^{m} B_i \\ & < \sum_{i=1}^{m-1} r_i^{\ast}\tau_s - \sum_{i=1}^{m-1} B_i \\ & \le\,0 \end{array} $$

Thus, $\mu_{1,m}^{\ast} = 0$ or slot m does not end with an empty buffer. Similarly, the reverse case, i.e., $\mu_{1,m}^{\ast} > 0$ implying $\mu_{3,m}^{\ast}=0,$ can also be derived. In other words, any slot m ∈ [1,...,M] can not be idle and end with an empty buffer at the same time. The second condition, $\mu_{1,m}^{\ast} \mu_{2,m}^{\ast}=0, m=D,\ldots,M,$ is due to the fact that if $\mu_{1,m}^{\ast} > 0,$ slot m must satisfy $h_{1,m}(\vec{r}^{\ast})=0,$ i.e., it must end with an empty buffer,

$$ \begin{array}{lll} h_{2,m}(\vec{r}^{\ast}) & =\sum_{i=1}^{m-D+1} B_i-\sum_{i=1}^{m} r_i^{\ast}\tau_s \\ & =-\sum_{i=m-D+2}^m B_i - h_{1,m}(\vec{r}^{\ast}) \\ & =-\sum_{i=m-D+2}^m B_i \\ & < \,0 \end{array} $$

Hence, $\mu_{2,m}^{\ast} = 0.$ Similarly, if $\mu_{2,m}^{\ast} > 0,$ we have $\mu_{1,m}^{\ast} = 0.$ In other words, any slot m ∈ [D,...,M] cannot be a delay-critical slot and ends with an empty buffer at the same time.

For the third condition, first note that an idle slot may possibly be a delay-critical slot, i.e., $h_{2,m}(\vec{r}^{\ast}) = \sum_{i=1}^{m-D+1} B_i-\sum_{i=1}^{m} r_i^{\ast}\tau_s$ and $r_m^{\ast}=0$ may be satisfied simultaneously, such that

$$ \mu_{2,m}^{\ast} \mu_{3,m}^{\ast} > 0. $$

However, if slot m + 1 is idle, slot m cannot be delay-critical, and vice versa, as indicated by condition $3\; (\mu_{2,m}^{\ast} \mu_{3,m+1}^{\ast}=0, m=D,\ldots,M+D-2).$ Consider if $\mu_{2,m}^{\ast} > 0,$ we have $h_{2,m}^{\ast}=0$ and hence slot m is delay-critical. That is, slot m ends with completing transmission of packets arrived at slot m − D + 1. Since B _m−D+1 > 0, for m = D,...,M + D − 1, slot m + 1 has to at least serve packets arrived at slot m − D + 2 and thus can not be idle, or $\mu_{3,m+1}^{\ast}=0.$ Similarly, one can also show that if $\mu_{3,m+1}^{\ast} > 0,$ we must have $\mu_{2,m}^{\ast}=0.$

Appendix C: Proof of Lemmas 2–5

For Lemma 2, since $r_m^{\ast} > 0$ and $r_{m+1}^{\ast} > 0,$ we have $\mu_{3,m}^{\ast}=\mu_{3,m+1}^{\ast}=0.$ Case 1 is further due to an empty buffer at the end of slot m, and hence a non delay-critical slot such that $\mu_{2,m}^{\ast}=0$ in (6). Case 2 is further due to $\mu_{1,m}^{\ast}=0$ as slot m is delay-critical and hence non-empty ending. Case 3 is further due to $\mu_{1,m}^{\ast}=0$ and $\mu_{2,m}^{\ast}=0$ as slot m is neither empty-ending nor delay-critical.

For Lemma 3, Case 1 is due to $\mu_{3,m+1}^{\ast}=0$ (non-idling slot) and $\mu_{1,m}^{\ast}=0$ (non-empty ending slot) in (6). Case 2 is due to $\mu_{3,m}^{\ast}=0$ (non-idling slot) and the last condition in (5), i.e., slot m can not be delay-critical if slot m + 1 is idle.

For Lemma 4, Case 1 is due to $\mu_{3,m+l}^{\ast}=0$ (non-idling slot) and $\mu_{1,i}^{\ast}=0, i=m,\ldots,m+l-1$ (idling slots can not be empty-ending), while Case 2 is due to $\mu_{3,m}^{\ast}=0$ (non-idling slot) and $\mu_{2,i}^{\ast}=0, i=m,\ldots,m+l-1$ (an idling slot can not be preceded by a delay-critical slot) in (7).

For Lemma 5, since $r_m^{\ast} > 0$ and $r_{m+l}^{\ast} > 0,$ we have $\mu_{3,m}^{\ast}=\mu_{3,m+l}^{\ast}=0.$ Case 1 is further due to $\mu_{2,i}^{\ast}=0, i=m,\ldots,m+l-2$ (as slots i = m + 1,...,m + l − 1 are idle), and $\mu_{2,m+l-1}^{\ast}=0$ (non delay-critical) in (7). Case 2 is further due to $\mu_{1, m}^{\ast}=0$ (non empty-ending), and $\mu_{1,i}^{\ast}=0, i=m+1,\ldots,m+l-1$ (as slots i = m + 1,...,m + l − 1 are idle) in (7). The last case is further due to the combination of Case 1 and Case 2 (i.e., $\mu_{1,i}^{\ast}=0$ and $\mu_{2,i}^{\ast}=0,\,\, i=m,\ldots,m+l-1).$

Appendix D: Packet delay lower and upper bounds

First, denote t _start,m as the time when the first bit of packet m is transmitted. Specially, let $t_{start,1}=0$ because from a delay perspective, if there are any idling periods before the first packet transmission, the first packet is effectively delayed starting from time 0. Similarly, denote $t_{end,m}$ as the departure time of the last bit of packet m’s transmission. Note that both $t_{start,m}$ and $t_{end,m}$ are not necessarily aligned with slot boundaries. Also, $t_{start,m}\,{\ge}\,t_{end,m-1},$ and the equality holds only if there is no idling period between the departure time of packet m − 1 and the start time of packet m’s transmission. By defining the inter-departure time of packet $m,{\,\,}m\in[1,\ldots,M],$ as $\phi_m\,\triangleq\, t_{end,m}-t_{end,m-1},$ with $t_{end,0}\,\triangleq\, 0,$ the delay for packet m can thus be computed as

$$ q_m=\sum_{l=1}^m\phi_l - (m-1)\tau_s, $$

where $\sum_{l=1}^m\phi_l=t_{end,m}$ and $(m-1)\tau_s$ are the departure time and the arrival time of packet m, respectively.

Now, define the virtual start time of packet $m\in[1,\ldots,M]$ as $t_{start,m}^v\,\triangleq\,(t_{end,m-1}+t_{start,m})/2,$ and the virtual departure time of packet $m\in[1,\ldots,M-1]$ as $t_{end,m}^v\,\triangleq\,(t_{end,m}+t_{start,m+1})/2.$ Let $t_{end,M}^v\,\triangleq\, (M+D-1)\tau_s,$ regardless of any potential idling slots after $t_{end,M}.$ Subsequently, define the virtual inter-departure time of packet m as

$$ \phi_m^v \,\triangleq\, t_{end,m}^v - t_{start,m}^v. $$

Note that if there are no idling slots between $t_{end}(m-1)$ and $t_{start}(m),$ and between $t_{end}(m)$ and $t_{start}(m+1),\,\, \phi_m^v$ corresponds to $\phi_m.$ Otherwise, $\phi_m^v$ also incorporates half of the idling period between $t_{end}(m-1)$ and $t_{start}(m),$ and half of the idling period between $t_{end}(m)$ and $t_{start}(m+1),$ for $2{\,\le\,}m {\,\le\,}M-1.$ For the first packet, $\phi_1^v$ includes the entire idling period, if any, before its transmission, while for the last packet, $\phi_m^v$ includes the entire remaining idling period after $t_{end}(M),$ if any. Denote

$$ q_m^v=\sum_{l=1}^m\phi_l^v - (m-1)\tau_s. $$

Note that since $t_{end,m}^v = t_{start,m+1}^v$ and $t_{end,m}^v \,\ge\, t_{end,m},$ we have $q_m^v \,\ge\, q_m.$

Due to the symmetry property of $\vec{B}$ and hence $\vec{r}^{\ast},$ as in Theorem 3, it is not difficult to show that, using a sample path trajectory of the forward running system and the corresponding time reversed system, the same symmetry property holds for the virtual inter-departure time vector $\vec{\phi}^{v}$ as well, i.e.,

$$ E\{\phi_m^v\} = E\{\phi_{M+1-m}^v\}, \forall m. $$

Therefore,

where (a) holds by counting the number of occurrences of each item, the first term of (b) comes from the symmetry property $E\{\phi_m^v\}=E\{\phi_{M-m+1}^v\},\forall m\in[1,\ldots,M],$ and equivalently, there are $(M+1)/2$ copies of each $E\{\phi_m^v\},$ and the first term of (c) is due to the fact that $\sum_{m=1}^M E\{\phi_m^v\} = (M+D-1)\tau_s.$

On the other hand, re-writing the average delay computation as

$$ \begin{array}{lll} \bar{q}(M) & \,\triangleq\, \frac{1}{M}\sum_{m=1}^ME\{q_m\} \\ & =E\{\frac{1}{M}\sum_{m=1}^M \sum_{l=1}^m\phi_l\}-\frac{1}{M}\sum_{m=1}^M (m-1)\tau_s \end{array} $$

we can see that $\sum_{l=1}^m \phi_l = t_{end,m}$ is used only once for each $m\in[1,\ldots,M]$ before taking the average ($1/M$) and the expectation. Similar statement also holds true for $\sum_{l=1}^m \phi_l^v = t_{end,m}^v$ as in (16). To quantify the difference between $t_{end,m}^v$ and t _end,m , denote

$$ \Updelta t_m^v \,\triangleq\, t_{end,m}^v-t_{end,m} = (t_{start}(m+1)-t_{end}(m))/2\,\ge\, 0. $$

First note that any idling periods between time 0 and t _start (1), and in between a packet transmission have no impact on $\Updelta t_m^v,\,\, \forall m.$ For a particular $m\in[1,\ldots,M-1],$ if there is one or more idle slot between $t_{end}(m)$ and $t_{start}(m+1),$ Δt ^v _m  > 0 and it equals to half of the idling period. However, any other idling periods between t _end (j) and t _start (j + 1),   j ≠ m, have no impact on $\Updelta t_m^v.$ In the special case of m = M, if there are idling slots after packet M transmission, we have $\Updelta t_M^v = (M+D-1)\tau_s-t_{end,M}.$ However, due to the symmetry property, there must exist a realization of the same length of an idling period between time 0 and t _start (1) (which does not impact $\Updelta t_1^v).$ Effectively, the idling period after t _end,M , if any, only contributes half of its duration to $\Updelta t_m^v.$ Therefore, we have:

Lemma 7

Any idling period effectively at most contributes once to the difference in the average delay computation using $\vec{\phi}^v$ and $\vec{\phi},$ and the contribution is at most half of its duration.

This leaves us to count the total idling duration within M + D − 1 slots. Due to the delay constraint D, there are at least $\left\lfloor (M+D-1)/D \right\rfloor\,\ge\,M/D$ non-idling slots between slots 1 and M + D − 1. Therefore, we have,

$$ \sum_{m=1}^{M} \left\{ \sum_{i=1}^m (\phi_i^v-\phi_i)\right\}\,\le\,\tau_s[(M+D-1-M/D)/2] $$

Defining

$$ \begin{array}{lll} \delta & \,\triangleq\, \tau_s[(M+D-1-M/D)/2]/M \\ & =\tau_s[(1-1/D)+(D-1)/M]/2, \end{array} $$

we finally have

$$ \bar{q}(M)\,\ge\,\tau_s\left[1+\frac{M+1}{2M}(D-1)\right] - \delta = \tau_s\left[\frac{D}{2}+\frac{1}{2D}\right]. $$

Note that δ converges to 0.5τ _s (1 − 1/D) when M approaches infinity.

In case of static channels, there will be no idling periods under the optimal offline schedule. Thus, ϕ _m =  ϕ ^v _m , and the equality holds in (16).