Embedded systems with multi-core designs are becoming increasingly important for signal processing and multimedia applications. While embedded multi-core systems will look to play an important role ahead for application designs, many challenging problems remain to be solved. Applications, programming models, compilers, architecture designs, and software tools all need to contribute to the advance of embedded multi-core computing for signal processing and multimedia applications.

The special issue on “Embedded Multicore Systems and Applications” brings together a rich blend of theory and practice in embedded computer architecture, parallel algorithms, runtime systems, compilers, networking, and performance evaluation. After each submission was reviewed by at least 3 experts and associate editors, the guest editors decided to accept 6 papers.

The first paper, “An Adaptive Heterogeneous Runtime Framework for Irregular Applications” (10.1007/s11265-014-0916-x), by Kao et al., is focused on managing the heterogeneous computing resources for the irregular applications. This paper presents a phase guided dynamic work partitioning framework for efficient work dispatching on a heterogeneous system. Such an approach tries to resolve the control flow divergence and load imbalance issues in irregular applications. The paper evaluates a Ray-Tracing application with the proposed method and shows significant performance gain.

There are three papers related to performance and power optimizations for multi-core embedded computing in this special issue. The paper titled “An Auto-tuning Assisted Power-Aware Study of Iris Matching Algorithm on Intel’s SCC” (10.1007/s11265-014-0901-4), authored by Torres et al., employed an Intel Single-chip Cloud Computer (SCC) to investigate the power-aware computing and performance enhancement of an iris matching algorithm on many-core architectures. The authors study various metrics and analyzed the results with different system parameters, including performance, power, energy, energy delay product, and power per speedup. Finally, they propose an auto-tuning method for quickly approaching the optimal configuration of the SCC based on the targeted metric.

The paper “Compilers for Low Power with Design Patterns on Embedded Multicore Systems” (10.1007/s11265-014-0917-9), by Lin et al., presents a set of power optimization schemes in compiler by exploiting the recurring patterns of embedded multicore applications. In this paper, the authors present a series of pattern-based pragmas to identify a specific parallel pattern for guiding compiler for power optimization. In their experiments, several multicore applications are evaluated with the proposed power optimization methods and have shown significant energy reduction.

The third paper in the category of performance and power optimizations, “Performance and Energy Evaluation of Different Multi-Threading Interfaces in Embedded and General Purpose Systems” (10.1007/s11265-014-0925-9), authored by Lorenzon et al., presents a detailed study on how the multi-threading programming interfaces influence on performance, energy, and energy delay product in embedded and general systems. Three major APIs, OpenMP, MPI, and Pthread are evaluated with 8 benchmarks that contain both CPU- and memory-bound programs.

The paper entitled “Multi-core DSP-based Vector Set Bits Counter/Comparators” (10.1007/s11265-014-0915-y), authored by Sklyarov et al., presents a hardware accelerator solution for fast counting and comparing vector bits which are also known as Hamming weights and Hamming distance. The proposed solution is based on multicore FPGA-based accelerators. Detailed hardware specification is given for analyzing and comparing with best known hardware/software solutions. They evaluate the proposed design and show significant speed-up while comparing to the known hardware/software alternatives.

The last paper in this special issue, titled “RCSoS: An IEC 61508 Compatible Server Model for Reliable Communication” (10.1007/s11265-014-0914-z), authored by Zhou et al., proposes a server model that utilizes the synergistic processor unit (SPU) in Cell/B.E. platform for reliable communication. Their building process confirms IEC 61508, which is an international standard that standardizes the functional safety for safety-related systems. The experimental results show the stable and acceptable performance of the proposed server model.

The above six papers in this special issue cover different aspects of multi-core embedded computing and applications for signal processing. These papers provide frontier information related to the embedded computer architecture, parallel algorithms, runtime systems, compilers, networking, and performance evaluation in the embedded multi-core computing for signal processing systems.