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Parallel High Throughput Soft-Output Sphere Decoding Algorithm

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Abstract

Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. To speed up the computation, we propose a scheme with multiple fixed complexity sphere decoders to construct a parallel soft-output fixed complexity sphere decoder (PFSD). The proposed decoder is highly parallel and has performance comparable to soft-output list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate that the PFSD algorithm can increase the throughput and reduce bit error rate of a soft-output solution in a 4 × 4 16-QAM system, and has superior performance compared to other soft decoders with comparable throughput and computation complexity. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can achieve up to 75 Mbps throughput for 4 × 4 64-QAM configuration at 100MHz with low control overhead.

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  1. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, 85287-5706, USA

    Qi Qi & Chaitali Chakrabarti

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  1. Qi Qi
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  2. Chaitali Chakrabarti
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Correspondence to Qi Qi.

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Qi, Q., Chakrabarti, C. Parallel High Throughput Soft-Output Sphere Decoding Algorithm. J Sign Process Syst 68, 217–231 (2012). https://doi.org/10.1007/s11265-011-0602-1

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  • DOI: https://doi.org/10.1007/s11265-011-0602-1

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