Skip to main content
Log in

Reconfigurable Blocks Based on Balanced Ternary

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Silicon-on-Insulator CMOS fabrication technologies are now available that offer a number of unique advantages including the availability of multiple simultaneous transistor thresholds. This paper proposes and analyzes a number of circuits for a reconfigurable array organization based on a balanced ternary logic system in which the logic set {− 1, 0, + 1} maps directly to equivalent voltage levels {−1V, 0V, +1V}. A number of low-power, high-speed components, such as a ternary buffer, flip-flop and look-up table, are described and simulated based on the characteristics of a commercially available silicon-on-sapphire process. A brief analysis indicates that the circuits will be capable of operating at the 22 nm technology node and beyond. A simple example of a Sigma-Delta Modulated FIR filter is mapped to the array and some preliminary estimates are made of its performance and area based on both 3-input and 4-input look-up tables. The simulated ternary array is shown to be capable of operating at clock speeds of more than 200 MHz such that it will readily support standard video bandwidths at useful over-sampling ratios.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18

Similar content being viewed by others

References

  1. Knuth, D. E. (1981). The art of computer programming, (Vol. 2). Reading, Mass.: Addison-Wesley Publishing Company.

  2. Wong, P. (1992). Fully sigma-delta modulation encoded FIR filters. IEEE Transactions on Signal Processing, 40(6), 1605–1610.

    Article  Google Scholar 

  3. Alexander, W. (1964). The ternary computer. Electronics and Power, 10(2), 36–39.

    Article  Google Scholar 

  4. Beckett, P. (2009). Towards a balanced ternary FPGA. In International conference on field-programmable technology, FPT 2009 (pp. 46–53).

  5. DeHon, A. (1996). Reconfigurable architectures for general-purpose computing. MIT A.I. Technical Report 1586.

  6. Sapphicon Semiconductor (2010). Available: http://www.sapphicon.com/.

  7. SIA (2009). International technology roadmap for semiconductors, process integraton devices and structures, 2009. Semiconductor industry association. Available: http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_PIDS.pdf.

  8. The Mosis Service (1981). Available: http://www.mosis.com/

  9. Thompson, A., O’Shea, P., Hussain, Z., & Steele, B. (2004). Efficient single-bit ternary digital filtering using sigma-delta modulator. IEEE Signal Processing Letters, 11(2), 164–166.

    Article  Google Scholar 

  10. Thompson, A. C., Hussain, Z. M. & O’Shea, P. (2005). A single-bit narrow-band bandpass digital filter. Australian Journal of Electrical and Electronics Engineering, 2(1), 31–40.

    Google Scholar 

  11. Sadik, Z., Hussain, Z. M., & O’Shea, P. (2006). An adaptive algorithm for ternary filtering. IEE Electronics Letters, 42(7), 420–421.

    Article  Google Scholar 

  12. Rajashekhara T., & Chen, I.-S. (1990). A fast adder design using signed-digit numbers and ternary logic. In Proceedings of the 1990 IEEE Southern Tier technical conference (pp. 187–194).

  13. Srivastava A., & Venkatapathy, K. (1996). Design and implementation of a low power ternary full adder. VLSI Design, 4(1), 75–81.

    Article  Google Scholar 

  14. Shibata T., & Ohmi, T. (1992). A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Transactions on Electron Devices, 39(6), 1444–1455.

    Article  Google Scholar 

  15. Gundersen H., & Berg, Y. (2006). A novel balanced ternary adder using recharged semi-floating gate devices. In ISMVL ’06: Proceedings of the 36th international symposium on multiple-valued logic (p. 18). Washington: IEEE Computer Society.

  16. Felicijan T., & Furber, S. (2003). An asynchronous ternary logic signaling system. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(6), 1114–1119.

    Article  Google Scholar 

  17. Philippe, J.-M., Kinvi-Boh, E., Pillement, S., & Sentieys, O. (2006). An energy-efficient ternary interconnection link for asynchronous systems. In Proceedings of the IEEE international symposium on circuits and systems, ISCAS 2006 (pp. 1011–1014).

  18. Duan C., & Khatri, S. P. (2008). Energy efficient and high speed on-chip ternary bus. In DATE ’08: Proceedings of the conference on design, automation and test in Europe (pp. 515–518). New York: ACM.

    Chapter  Google Scholar 

  19. Sipos, E., Festila, L., & Oltean, G. (2008). Towards reconfigurable circuits based on ternary controlled analog multiplexers/demultiplexers. In I. Lovrek, R. Howlett, & L. Jain (Eds.), Lecture Notes in computer science: Knowledge-based intelligent information and engineering systems (Vol. 5179). Berlin/Heidelberg: Springer-Verlag.

    Google Scholar 

  20. Kang, S.-M., & Leblebici, Y. (1996). CMOS digital integrated circuits: Analysis and design. McGraw-Hill.

  21. Kuhn, K., Kenyon, C., Kornfeld, A., Liu, M., Maheshwari, A., kai Shih, W., et al. (2008). Managing process variation in Intel’s 45 nm CMOS technology. Intel Technology Journal, 12(2), 93–109.

    Google Scholar 

  22. Calhoun, B., Khanna, S., Mann, R., & Wang, J. (2009). Sub-threshold circuit design with shrinking cmos devices. In IEEE international symposium on circuits and systems, ISCAS 2009 (pp. 2541–2544).

  23. Tsunomura, T., Nishida, A., Yano, F., Putra, A., Takeuchi, K., Inaba, S., et al. (2009). Analysis of extra vt variability sources in nmos using takeuchi plot. In IEEE symposium on VLSI technology (pp. 110–111).

  24. Andrieu, F., Weber, O., Mazurier, J., & Faynot, O. (2010). Planar fully depleted SOI: Technological solution against variability, solid state technology. Available: http://online.qmags.com/SST1110.

  25. Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss, J., Shahrjerdi, D., et al. (2009). Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In IEEE international electron devices meeting (IEDM 2009) (pp. 1–4).

  26. Connell, C., & Balsara, P. (2001). A novel single-rail variable encoded completion detection scheme for self-timed circuit design using ternary multiple valued logic. In Proceedings of the IEEE 2nd Dallas CAS workshop on low power/low voltage mixed-signal circuits and systems, 2001. (DCAS-01) (pp. P7–10).

  27. Betz, V., & Rose, J. (1998). How much logic should go in an FPGA logic block? IEEE Design and Test of Computers, 15(1), 10–15.

    Article  Google Scholar 

  28. Ahmed, E., & Rose, J. (2004). The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3), 288–298.

    Article  Google Scholar 

  29. Chu, K. M., & Pulfrey, D. (1986). Design procedures for differential cascode voltage switch circuits. IEEE Journal of Solid-State Circuits, sc-21(6), 1082–1087.

    Article  Google Scholar 

  30. Fan, H., Liu, J., Wu, Y.-L., & Cheung, C.-C. (2001). On optimum switch box designs for 2-D FPGAs. In Proceedings of the design automation conference, DAC 2001 (pp. 203–208).

  31. Fan, H., & Wu, Y.-L. (2005). Crossbar based design schemes for switch boxes and programmable interconnection networks. In Proceedings of the Asia and South Pacific design automation conference, ASP-DAC 2005 (Vol. 2, pp. 910–915).

  32. Brayton, R., & Khatri, S. (1999). Multi-valued logic synthesis. In Proceedings of the twelfth international conference on VLSI design (pp. 196–205).

  33. Memon, T. D., Beckett, P., & Hussain, Z. M. (2009). Design and implementation of ternary fir filter using sigma delta modulation. In Proceedings of the international symposium on computing, communication, and control (ISCCC’09).

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Paul Beckett.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Beckett, P., Memon, T. Reconfigurable Blocks Based on Balanced Ternary. J Sign Process Syst 67, 3–13 (2012). https://doi.org/10.1007/s11265-010-0559-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0559-5

Keywords

Navigation